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Converted signed 16 Bit to unsigned?

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elektroda.net NewsGroups Forum Index - VHDL Language - Converted signed 16 Bit to unsigned?

Steffen Koepf
Guest

Thu Dec 15, 2011 12:03 am   



Hello,

I have a AD Converter that delivers a 16 Bit signed value 8000 - 0 - 7FFF

I want to convert this to unsigned 16 Bit from 0 - 8000 - FFFF

by

signal RecRegA : std_logic_vector (15 downto 0);

signal RecRegA1 : std_logic_vector (15 downto 0);


RecRegA1 <= std_logic_vector(unsigned(RecRegA) + 32768);


This works in the lower 3/4 range. But as soon as the result exceeds 7FFF
the result is unpredictable. Why?

Thanks in advance,

Steffen

Gabor
Guest

Thu Dec 15, 2011 12:03 am   



Steffen Koepf wrote:
Quote:
Hello,

I have a AD Converter that delivers a 16 Bit signed value 8000 - 0 - 7FFF

I want to convert this to unsigned 16 Bit from 0 - 8000 - FFFF

by

signal RecRegA : std_logic_vector (15 downto 0);

signal RecRegA1 : std_logic_vector (15 downto 0);


RecRegA1 <= std_logic_vector(unsigned(RecRegA) + 32768);


This works in the lower 3/4 range. But as soon as the result exceeds 7FFF
the result is unpredictable. Why?

Thanks in advance,

Steffen


That's a lot of conversions. All you really need to do is invert the

MSB of the first vector. What libraries are you using?

-- Gabor

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