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Guest
Sun Jan 22, 2012 4:37 am
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
--
Cheers,
James Arthur
John Larkin
Guest
Sun Jan 22, 2012 5:02 am
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodboat_at_yahoo.com
wrote:
Quote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
John
George Herold
Guest
Sun Jan 22, 2012 5:45 am
On Jan 21, 9:37 pm, dagmargoodb...@yahoo.com wrote:
Quote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
I've got a TEC thermal control circuit where I had to run a separate
power return ground line.
Quote:
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS.
By hanging more C on the gate? a Tee RCR network?
George H.
That's
Quote:
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
Quote:
YMMV.
--
Cheers,
James Arthur
John Larkin
Guest
Sun Jan 22, 2012 6:03 am
On Sat, 21 Jan 2012 20:28:37 -0800 (PST), dagmargoodboat_at_yahoo.com
wrote:
Quote:
On Jan 21, 11:02 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
John
I sure wish they would.
Here, they've got up to 20A in loads, which they didn't want polluting
the a/d inputs on the logic board, I s'pose.
20 amps is small change. I prefer, whenever possible, to ground
everything to a PCB ground plane, and bolt that to the box at every
opportunity. Handle low-level signals properly, locally.
John
Guest
Sun Jan 22, 2012 6:12 am
On Jan 21, 10:45 pm, George Herold <gher...@teachspin.com> wrote:
Quote:
On Jan 21, 9:37 pm, dagmargoodb...@yahoo.com wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
I've got a TEC thermal control circuit where I had to run a separate
power return ground line.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS.
By hanging more C on the gate? <snip
No, that will be low impedance at high frequency, which risks
oscillation (forms a pi network with the gate bond wire inductance and
the internal capacitances). I just increased the gate resistor to
several K. Miller does the rest.
I thought about it long and hard first, and I think hi-z gate drive
avoids the various oscillation modes. That disrupts all the possible
tuned circuits at the gate that might provide phase shift, kills all
the Q's, and prevents high currents flowing anywhere. Still, it was
reassuring to try it in real life. It works.
--
Cheers,
James Arthur
George Herold
Guest
Sun Jan 22, 2012 6:12 am
On Jan 21, 11:02 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
Quote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
In my case I had a monitor voltage that went of to another board. The
TEC could draw an amp or two, which would put a bit of offset on the
monitor signal... I don't recall how much... 100's of uVs? Running
another power supply ground wire was an easy fix.
George H.
Quote:
John- Hide quoted text -
- Show quoted text -
Guest
Sun Jan 22, 2012 6:28 am
On Jan 21, 11:02 pm, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
Quote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
John
I sure wish they would.
Here, they've got up to 20A in loads, which they didn't want polluting
the a/d inputs on the logic board, I s'pose.
Part of my difficulty is that, if you imagine PWR_GND is an inductor,
which it is, hanging a tank on the gate makes a classic RF
oscillator. An ordinary resistive drive yields a lightly damped
impulse. Big.
Okay, so, on top of that ringing, I have a source-current sensing
resistor as part of protecting the FET, which I have to read bouncing
@ 250Khz.
I think it's whipped now. Ring amplitude way less, damping much
higher, settles faster. RFI reduced dramatically, too.
--
Cheers,
James Arthur
Guest
Sun Jan 22, 2012 6:43 am
On Jan 21, 11:12 pm, George Herold <gher...@teachspin.com> wrote:
Quote:
On Jan 21, 11:02 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
In my case I had a monitor voltage that went of to another board. The
TEC could draw an amp or two, which would put a bit of offset on the
monitor signal... I don't recall how much... 100's of uVs? Running
another power supply ground wire was an easy fix.
George H.
This system puts 10-20A on that wire. The architect is long gone, so
I can only guess his motivation was similar to yours. The logic board
is some distance from the system power supply, so running the load
currents through the logic board would put transients on the logic
board ground. To avoid that, he added a separate return.
Given that, I'd float and galvanically isolate the drive and sensing
circuits from the control logic, if it were up to me. Reference them
all to the FET. Driving a logic-level FET with an inductive source
load, from a driver on a different ground, is really asking for it.
Heavy damping / hi-z drive worked here, which is why I posted it--I've
not had this problem before, or seen a solution.
--
Cheers,
James Arthur
langwadt@fonz.dk
Guest
Sun Jan 22, 2012 7:09 am
On 22 Jan., 05:28, dagmargoodb...@yahoo.com wrote:
Quote:
On Jan 21, 11:02 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
John
I sure wish they would.
Here, they've got up to 20A in loads, which they didn't want polluting
the a/d inputs on the logic board, I s'pose.
Part of my difficulty is that, if you imagine PWR_GND is an inductor,
which it is, hanging a tank on the gate makes a classic RF
oscillator. An ordinary resistive drive yields a lightly damped
impulse. Big.
Okay, so, on top of that ringing, I have a source-current sensing
resistor as part of protecting the FET, which I have to read bouncing
@ 250Khz.
I think it's whipped now. Ring amplitude way less, damping much
higher, settles faster. RFI reduced dramatically, too.
--
Cheers,
James Arthur
plug in something like this
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000232.pdf
and you can skip the protection part, is kinda slow too so rfi should
be resonable
-Lasse
Robert Baer
Guest
Sun Jan 22, 2012 9:05 am
dagmargoodboat_at_yahoo.com wrote:
Quote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
--
Cheers,
James Arthur
Saw no mention of a local bypass cap AT the FET (source to +24V supply)..
Robert Baer
Guest
Sun Jan 22, 2012 9:06 am
John Larkin wrote:
Quote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodboat_at_yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
John
Not enough dirt??
Robert Baer
Guest
Sun Jan 22, 2012 9:08 am
dagmargoodboat_at_yahoo.com wrote:
Quote:
On Jan 21, 10:45 pm, George Herold <gher...@teachspin.com> wrote:
On Jan 21, 9:37 pm, dagmargoodb...@yahoo.com wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
I've got a TEC thermal control circuit where I had to run a separate
power return ground line.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS.
By hanging more C on the gate? <snip
No, that will be low impedance at high frequency, which risks
oscillation (forms a pi network with the gate bond wire inductance and
the internal capacitances). I just increased the gate resistor to
several K. Miller does the rest.
I thought about it long and hard first, and I think hi-z gate drive
avoids the various oscillation modes. That disrupts all the possible
tuned circuits at the gate that might provide phase shift, kills all
the Q's, and prevents high currents flowing anywhere. Still, it was
reassuring to try it in real life. It works.
--
Cheers,
James Arthur
But that decreases the drive current and (as you know) decreases the
turn-on / turn-off speeds.
Mark Datter
Guest
Sun Jan 22, 2012 3:08 pm
On Sun, 22 Jan 2012 05:29:28 -0800 (PST), dagmargoodboat_at_yahoo.com wrote:
Quote:
On Jan 22, 3:08 am, Robert Baer <robertb...@localnet.com> wrote:
dagmargoodb...@yahoo.com wrote:
On Jan 21, 10:45 pm, George Herold <gher...@teachspin.com> wrote:
On Jan 21, 9:37 pm, dagmargoodb...@yahoo.com wrote:
I'm updating an existing system.
The system had this:
But that decreases the drive current and (as you know) decreases the
turn-on / turn-off speeds.
Which was the goal. We usually switch FETs hard and fast; it was
interesting doing a controlled slew rate. Making a Miller integrator
makes a nice, clean, linear ramp.
This could find use in switchers, as per Jim Williams' LT1534;
occasionally a 1-2uS switching time wouldn't hurt the FET, doesn't
waste much power, and would clean up a lot of RFI.
We place a ferrite ring directly on the lead of the FET.
Bill Sloman
Guest
Sun Jan 22, 2012 3:12 pm
On Jan 22, 5:12 am, George Herold <gher...@teachspin.com> wrote:
Quote:
On Jan 21, 11:02 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Sat, 21 Jan 2012 18:37:05 -0800 (PST), dagmargoodb...@yahoo.com
wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
Why don't people just ground things?
In my case I had a monitor voltage that went of to another board. The
TEC could draw an amp or two, which would put a bit of offset on the
monitor signal... I don't recall how much... 100's of uVs? Running
another power supply ground wire was an easy fix.
In my published Peltier-based thermostat, we optically isolated the
MOSFET drivers from the rest of the circuit just to avoid having to
put the Peltier drive current through a shared ground return. Worked
fine.
Sloman A.W., Buggs P., Molloy J., and Stewart D. “A microcontroller-
based driver to stabilise the temperature of an optical stage to 1mK
in the range 4C to 38C, using a Peltier heat pump and a thermistor
sensor” Measurement Science and Technology, 7 1653-64 (1996)
During bug-hunting, my successor (Paul Buggs - a friend) temporarily
swapped out the switching drive for the Peltier junction and replaced
it with a linear driver we'd put together when we charactering various
candidate Peltier junctions and it didn't change the noise levels at
all, which were still dominated by processor noise.
--
Bill Sloman, Nijmegen
Guest
Sun Jan 22, 2012 3:19 pm
On Jan 22, 3:05 am, Robert Baer <robertb...@localnet.com> wrote:
Quote:
dagmargoodb...@yahoo.com wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
So, I've knocked down the slew rate. T(fall) = t(rise) = 3uS. That's
fast enough to avoid SOA problems, but <1/10th the current slew rate.
The inductive spike is reduced proportionally. I was concerned it
might scream at VHF or something, but it doesn't. Cleans up the
PWR_GND spike beautifully, of course.
YMMV.
--
Cheers,
James Arthur
Saw no mention of a local bypass cap AT the FET (source to +24V supply)..
Define "local". Bypass to which ground? There's a spider-web of
supply and ground wires. So, there's no way to "bypass" the loads to
a common reference, only to / through yet another inductive ground
wire.
Some of the loads have built-in bypass capacitors; that makes the load
happy, but the ground transient when you turn them on worse, of
course.
--
Cheers,
James Arthur
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