Jamie
Guest
Tue Jan 24, 2012 1:10 am
John Larkin wrote:
Quote:
On Mon, 23 Jan 2012 05:40:16 -0800 (PST), Fred Bloggs
bloggs.fredbloggs.fred_at_gmail.com> wrote:
On Jan 21, 9:37 pm, dagmargoodb...@yahoo.com wrote:
I'm updating an existing system.
The system had this:
+24v
|
.------.
| load |
|\ +3.3v '------'
| \| |
| \ ||-'
--| >---R1--||
| / ||>.
| /| |
|/=== '---< PWR_GND
driver
Where PWR_GND is a long wire to the system power supply, and "load" is
any one of a variety of resistive, inductive, and capacitive loads.
Nasty. I don't like all these different GNDs, but that's what I'm
handed.
The original circuit wasn't applying enough Vgs to guarantee
saturating the FET, so I increased Vdd to +5v. Okay, that works.
Next, the ~200nS switching time put a nnnnasty glitch on the 1-meter
long PWR_GND wire.
Twisting PWR_GND and the +24v supply line helped reduce inductance a
lot, cutting the gltich in better than half. Adding ferrites took
some of the edge off the current slew, further suppressing the glitch,
but it's still troublesome.
Ummm, twisting the supply and ground wires increases distributed C in
the sqrt(L/C) resulting transmission line, lowering the impedance.
At these currents, the C of the cable, tens of pF per foot, doesn't
matter. The advantage of twisting is reducing L.
John
You mean they configured in such a way to create a common mode choke?
I don't see how that really effects L other than canceling. UNless I
am not following something here ?
Jamie
