constants of sfixed in architecture body

Thu Jul 08, 2010 1:30 pm   

Hi,

in the example attached I did try to set some filter coeffs constants
for a fir filter (direct form I second order structure). Modelsim
complains on

Type mark "coeefficient_type" cannot be actual parameter.
Illegal name (subtype declaration "coeefficient_type") in expression.

Is there a limitation or simple a syntax error. Is there a way to do
this - how to get it?

Thanks,
Olaf


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library floatfixlib;
use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version

entity df1tsos is

port (
clk : in std_ulogic;
clk_en : in std_ulogic;
reset : in std_ulogic;
input : in sfixed(16 downto -14); -- [-2 2)
output : out sfixed(16 downto -14) -- [-2 2)
);

end entity df1tsos;

architecture rtl of df1tsos is

subtype numerator_type is sfixed(16 downto -14); -- [-2 2)
subtype denominator_type is sfixed(16 downto -14); -- [-2 2)
subtype numerator_state_type is sfixed(16 downto -12); -- [-8
subtype denominator_state_type is sfixed(16 downto -12); -- [-8
subtype coeefficient_type is sfixed(16 downto -14); -- [-2 2)

signal numerator_s : numerator_type;
signal denominator_s : denominator_type;

constant b0_coeff : coeefficient_type := to_sfixed(
0.000000000000000, coeefficient_type);
constant b1_coeff : coeefficient_type := to_sfixed(
1.000000000000000, coeefficient_type);
constant b2_coeff : coeefficient_type := to_sfixed(
0.843811035156250, coeefficient_type);
constant a0_coeff : coeefficient_type := to_sfixed(
1.000000000000000, coeefficient_type);
constant a1_coeff : coeefficient_type :=
to_sfixed(-1.538757324218750, coeefficient_type);
constant a2_coeff : coeefficient_type := to_sfixed(
0.601013183593750, coeefficient_type);

begin


end architecture rtl;

Thu Jul 08, 2010 2:22 pm   

constant b0_coeff : coeefficient_type := to_sfixed(
0.000000000000000, coeefficient_type'high, coeefficient_type'low);
constant b1_coeff : coeefficient_type := to_sfixed(
1.000000000000000, coeefficient_type'high, coeefficient_type'low);
constant b2_coeff : coeefficient_type := to_sfixed(
0.843811035156250, coeefficient_type'high, coeefficient_type'low);
constant a0_coeff : coeefficient_type := to_sfixed(
1.000000000000000, coeefficient_type'high, coeefficient_type'low);
constant a1_coeff : coeefficient_type :=
to_sfixed(-1.538757324218750, coeefficient_type'high,
coeefficient_type'low);
constant a2_coeff : coeefficient_type := to_sfixed(
0.601013183593750, coeefficient_type'high, coeefficient_type'low);

must it really be complicated?

Thanks,
Olaf

Thu Jul 08, 2010 4:54 pm   

On 8 July, 14:22, Paul <P...@noreply.com> wrote:

The function you are trying to call expects a declared object (so a
signal, variable or constant). you cannot pass types into functions.

you could do it with something like:

constant COEFF_SIZER : coeeffiecient_type;

constant a2_coeff : coeefficient_type := to_sfixed(0.724545,
COEFF_SIZER);

Just a quick question: are you sure you want such large coefficients
and data types, and ones that dont divide by 18? Altera multipliers
(and I think Xilinx too) work on 18 bit inputs (giving 36 bits
results). 2x 36bit inputs eats up 4 multipliers.

Fri Jul 09, 2010 7:11 am   

Thanks for your help,


got unfortunately the rror

Deferred constants are allowed only in a package declaration.

by modelsim. If I write

subtype coeefficient_type is sfixed(16 downto -14); -- [-2 2)

signal coeeffiecient_sizer : coeefficient_type;

constant b0_coeff : coeefficient_type := to_sfixed(
0.000000000000000, coeeffiecient_sizer);

Warning: value of "b0_coeff" depends on value of signal
"coeeffiecient_sizer". What are the consequences on this, is it fixable?



Thanks,
Olaf

Fri Jul 09, 2010 9:05 am   

why is it better to use data types which divide by 18? I want to use
Xilinx DSP48 slices on virtex4. My Coeffs have a width of 16bit (18 I
could use). Input is 16bit also, multiplying get 32 bit, DSP48's adder
has an input width of 48bit - there is room for sum results bigger than
1. I did scale my input to [1 1), my coeffs are [2 -2). Maybe I miss
something? I did wonder why they have 18bits.

BTW, my first implementation of fixed point arithmetic / FIR/IIR in FPGA :-)

Thanks,
Olaf

Fri Jul 09, 2010 10:40 am   

On 9 July, 07:11, Paul <P...@noreply.com> wrote:

Ooops, my bad. It needs an actual value. try this instead:
constant COEFF_SIZER : coeeffiecient_type := (others => '0');



Nothing for this function. This function only uses the sizing
attributes from the signal, not the actual value stored in the signal.