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Conditional compiling, exists ?

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LC
Guest

Tue Jan 19, 2010 3:03 pm   



Hi.

Sorry for the naive question.

Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

I would like to have a source with two variants
that I may decide to compile one way or another
but there are several small differences spread
across the code so...

(two separate files is difficult to maintain in sync
while design progresses)
(commenting and uncommenting parts is prone to mistakes
and messy)

Is there any hope to make my life easier ?


Luis. C.

Rich Webb
Guest

Tue Jan 19, 2010 4:35 pm   



On Tue, 19 Jan 2010 14:03:57 +0000, LC <cupidoREMOVE_at_mail.ua.pt> wrote:

Quote:
Hi.

Sorry for the naive question.

Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

I would like to have a source with two variants
that I may decide to compile one way or another
but there are several small differences spread
across the code so...

(two separate files is difficult to maintain in sync
while design progresses)
(commenting and uncommenting parts is prone to mistakes
and messy)

Is there any hope to make my life easier ?

You might want to look at "m4" which is a macro preprocessor intended as
a front end to the "normal" compilation process. It's a pretty standard
Unix utility (or did it pre-date Unix?) that's now on most (all?) *ix
distributions. There are binary versions for Windows (Cygwin and native
code) and Mac.

For more info, hop over to the Wikipedia entry and go from there.

--
Rich Webb Norfolk, VA

Petter Gustad
Guest

Tue Jan 19, 2010 4:57 pm   



LC <cupidoREMOVE_at_mail.ua.pt> writes:

Quote:
Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

See generate.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Tricky
Guest

Tue Jan 19, 2010 5:05 pm   



On 19 Jan, 14:03, LC <cupidoREM...@mail.ua.pt> wrote:
Quote:
Hi.

Sorry for the naive question.

Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

I would like to have a source with two variants
that I may decide to compile one way or another
but there are several small differences spread
across the code so...

(two separate files is difficult to maintain in sync
while design progresses)
(commenting and uncommenting parts is prone to mistakes
and messy)

Is there any hope to make my life easier ?

Luis. C.

I think there may be a couple of options:

1. Have 2 different architectures for the same entity and use
configurations to change which one to compile
2. Use generics to control what gets compiled based on the values:

for example:

reg_gen : if add_register generate

process(clk)
begin
if rising_edge(clk) then
out <= in;
end if;
end process;
end reg_gen

no_reg_gen : if not add_register generate

out <= in;
end no_reg_gen;


Given what you already said (2 variants on the same thing) you
probably want configurations (someone else will have to explain this
mystical VHDL concept).

Mike Treseler
Guest

Tue Jan 19, 2010 5:13 pm   



LC wrote:

Quote:
Is there a way to implement conditional compiling
in VHDL (as in C for example, #ifdef... #endif).

There is no preprocessor.
I use packaged constants with regular
vhdl conditional statements or generics.

-- Mike Treseler

LC
Guest

Wed Jan 20, 2010 2:24 pm   



Many thanks for the tips.

LC.

Alan Fitch
Guest

Wed Jan 20, 2010 5:04 pm   



LC wrote:
Quote:
Many thanks for the tips.

LC.

Hi LC,
we also have a little technote about this very issue:

http://www.doulos.com/knowhow/fpga/technotes/index.php#Technote2

regards
Alan

P.S. We ask you to register for it - but as I remember there's a tickbox
somewhere for you to opt out of being contacted again if you don't want
to be, Alan


--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

------------------------------------------------------------------------

This message may contain personal views which are not the views of
Doulos, unless specifically stated.

LC
Guest

Thu Jan 21, 2010 12:59 am   



Alan Fitch wrote:
Quote:
LC wrote:
Many thanks for the tips.

LC.

Hi LC,
we also have a little technote about this very issue:

http://www.doulos.com/knowhow/fpga/technotes/index.php#Technote2

regards
Alan

P.S. We ask you to register for it - but as I remember there's a tickbox
somewhere for you to opt out of being contacted again if you don't want
to be, Alan



Hi Alan,

I could not imagine a better technote on the subject Smile
You guys rock !

Many Thanks.

Luis C.

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