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Close Timing and STA

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elektroda.net NewsGroups Forum Index - Synthesis - Close Timing and STA

Anand P. Paralkar
Guest

Fri Jan 06, 2006 7:33 pm   



Hi,

I would like to know:

a. What is meant by "Close Timing" for an ASIC, and,
b. What are the typical tasks that an STA engineer does?
(I know a. above, could be an answer, but I am looking
for a little more detailed answer. Smile )

(Request you to support your explaination with examples.)

Thanks,
Anand


Guest

Sun Jan 08, 2006 7:06 am   



Timing closure is to fix setup/hold timing violations.
STA's job is to set good constrain and find all violations. Then do
timing ECO. Timing ECO is the hard part.
You can take a look at an example of using netlist processing tool GOF
to do Timing ECO
http://www.nandigits.com/timing_eco.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode


Guest

Mon Jan 09, 2006 12:34 am   



Timing closure is to fix setup/hold timing violations.
STA's job is to set good constrain and find all violations. Then do
timing ECO. Timing ECO is the hard part.
You can take a look at an example of using netlist processing tool GOF
to do Timing ECO

http://www.nandigits.com/timing_eco.htm

Nandy


Guest

Mon Jan 09, 2006 2:33 am   



Timing closure is to fix setup/hold timing violations.
STA's job is to set good constrain and find all violations. Then do
timing ECO. Timing ECO is the hard part.
You can take a example of using netlist processing tool GOF to do
Timing ECO
http://www.nandigits.com/timing_eco.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.


Guest

Mon Jan 09, 2006 4:20 am   



Timing closure is to fix setup/hold timing violations.
STA's job is to set good constrain and find all violations. Then do
timing ECO. Timing ECO is the hard part.
You can take a look at an example of using netlist processing tool GOF
to do Timing ECO
http://www.nandigits.com/timing_eco.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.


Guest

Mon Jan 09, 2006 4:23 am   



Close timing is to fix setup/hold time violations in pre-layout and
post-layout netlist.
STA's job is to write good constrains and find out all true violations.
And do timing ECO to fix these violations. Timing ECO is the hard part
of the job.
You can take a look at following link to see a timing ECO example by
using netlist processing tool GOF.
http://www.nandigits.com/timing_eco.htm


Nandy

elektroda.net NewsGroups Forum Index - Synthesis - Close Timing and STA

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