Clock Frequency Synthesis

On Jan 26, 7:55 pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:









On 26 Jan., 18:52, Bill Sloman <bill.slo...@ieee.org> wrote:

On Jan 26, 4:19 pm, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman

bill.slo...@ieee.org> wrote:
On Jan 26, 6:46 am, spflanze <art...@wavenet.org> wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ....
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the
programmable logic of your choice.

--
Bill Sloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

From a battery? At least with programmable logic, every switching
event is one that you have programmed.

--
Bill Sloman, Nijmegen

On Jan 26, 1:52 pm, George Herold <gher...@teachspin.com> wrote:





On Jan 26, 3:58 pm, spflanze <art...@wavenet.org> wrote:

On Jan 26, 7:08 am, George Herold <gher...@teachspin.com> wrote:

On Jan 26, 2:37 am, Tim Wescott <t...@seemywebsite.please> wrote:

On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:
I need to design a sine wave synthesizer for six channels. Each channel
must have a different frequency and be an exact multiple of 1Hz..
Frequency ranges are from 100Hz to 1Khz.

I will do this by filtering out the harmonics of a square wave with an
MAX294 switched capacitor filter:
http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdfIwillneedto
clock each of the six filter chips at approximately 167 times the
frequency of the square wave to be filtered. This is to get the third
harmonic in the notch shown at 1.8kHz in the MAX294 frequency response
curve on page 4.

Before I look into programing the dividers and timers into an FPGA to
synthesize these 12 frequencies from a single reference frequency I am
looking for off the shelf logic that can do this in just a few chips.
What can you suggest?

The sine waves will be used to drive LEDs that illuminate optrodes. It
is expected there will be a small amount of light crosstalking into the
other channels. The crosstalk will be eliminated by FFT on the output of
the photodiode's TIA. Maximum suppression of crosstalk will happen when
the channel frequencies are a multiple of 1/T where T is the length of
time the transform is done over. T can be 100 ms, 200 ms, 500 ms or 1 s.

I suggest that you ditch the idea of doing it with a switched capacitor
filters and frequency synthesis, and instead do it by direct digital
synthesis and some ADCs.  One reasonably fast microprocessor (32-bit ARM
Cortex) should be able to handle six channels with ease.

--
Tim Wescott
Control system and signal processing consultingwww.wescottdesign.com-Hidequotedtext-

- Show quoted text -

I've only used a switched cap filters once.  LTC1063.  There were
(what we called) intermodulation distortion at the ~45-50dB level.  It
took a while to identify the SCF as the source.

Switched cap filters sound so nice 'in theory'.

To the spflanze; why so low frequencies?  Wouldn't it be easier to
work up at maybe the 10kHz range... and put 1kHz (or so) between
channels?   And then forget about the harmonics.  Or one nice analog
low pass after the photodiodes to kill them all.

George H.

The frequencies are chosen where I expect the noise in the system to
be lowest. This is above the TIA's 1/f noise corner and beneath the
zero created by the capacitance around the TIA's inverting input and
feedback resistor. The frequencies of the six channels are not the
same because I am expecting a little bit of the LED light to crosstalk
between channels. All six optrode chemistries are on the same glass
slide.

Your TIA and photodiode have a 3dB point near 1kHz?  Big photodiode
(PD)?
Large feedback resistance?  Are you reverse biasing the PD?
It will pay you big time to make the front end faster.

More light (lower feedback R)
PD no bigger than you need (lower C)
reverse bias the PD (lower C)
faster opamp.  (max TIA freq goes as sqrt of opamp GBW)

Then for more exotic tricks you can bootstrap the PD,
or try Phil Hobb's cascode on the front end.
Both are attempts to reduce the effects of the PD capacitance.

George H.

The feedback resistor is not known yet and will not be known until it
is used. A digital potentiometer will be used in the feedback path
because of this. So the location of the zero is not known now.

I want all six channels to be near the 1/f noise corner. For
exceptional opamps this can be as low as 300Hz. For a typical op amp
used for a TIA it could be as high as 1kHz.

I know about reducing PD capacitance. Besides the way Phil Hobbs does
it, another way is the bootstrap with the JFET shown here:http://www.linear.com/product/LTC6244
Other bootstrap circuits are described in "Photodiode Amplifiers" by
Jerald Graeme.

Photodiode capacitance can be reduced but not eliminated. And there
are other capacitances besides the photodiode. The zero will exist no
matter what. Wherever it is I want to stay under it.- Hide quoted text -

- Show quoted text -

On Jan 27, 12:03 am, spflanze <art...@wavenet.org> wrote:
On Jan 26, 1:36 pm, Bill Sloman <bill.slo...@ieee.org> wrote:









On Jan 26, 7:55 pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:

On 26 Jan., 18:52, Bill Sloman <bill.slo...@ieee.org> wrote:

On Jan 26, 4:19 pm, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman

bill.slo...@ieee.org> wrote:
On Jan 26, 6:46 am, spflanze <art...@wavenet.org> wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the
programmable logic of your choice.

--
Bill Sloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

From a battery? At least with programmable logic, every switching
event is one that you have programmed.

--
Bill Sloman, Nijmegen

If the timers on the processor can do the job it will greatly reduce
the number of counter chips I have on the board. Its clock rate is
much slower than the Blackfin but the FPU might make up for that. I am
looking at it.

Use a single - big-enough - programmable logic device and bury all
your counters (and the rest of the logic) inside it.

I've got a weakness for the Xilinx CoolRunner parts - they don't draw
much current at all. I've never actually been able to use one - not
for want of trying (I've got 15 of then in my desk drawer) - but they
look good.

http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

On Jan 26, 1:36 pm, Bill Sloman <bill.slo...@ieee.org> wrote:









On Jan 26, 7:55 pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:

On 26 Jan., 18:52, Bill Sloman <bill.slo...@ieee.org> wrote:

On Jan 26, 4:19 pm, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman

bill.slo...@ieee.org> wrote:
On Jan 26, 6:46 am, spflanze <art...@wavenet.org> wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the
programmable logic of your choice.

--
Bill Sloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

From a battery? At least with programmable logic, every switching
event is one that you have programmed.

--
Bill Sloman, Nijmegen

If the timers on the processor can do the job it will greatly reduce
the number of counter chips I have on the board. Its clock rate is
much slower than the Blackfin but the FPU might make up for that. I am
looking at it.

On Thu, 26 Jan 2012 12:58:59 -0800, spflanze wrote:
On Jan 26, 7:08 am, George Herold <gher...@teachspin.com> wrote:
On Jan 26, 2:37 am, Tim Wescott <t...@seemywebsite.please> wrote:

On Wed, 25 Jan 2012 21:46:51 -0800, spflanze wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

I will do this by filtering out the harmonics of a square wave with
an MAX294 switched capacitor filter:
http://datasheets.maxim-ic.com/en/ds/MAX293-MAX297.pdfIwillneed to
clock each of the six filter chips at approximately 167 times the
frequency of the square wave to be filtered. This is to get the
third harmonic in the notch shown at 1.8kHz in the MAX294 frequency
response curve on page 4.

Before I look into programing the dividers and timers into an FPGA
to synthesize these 12 frequencies from a single reference
frequency I am looking for off the shelf logic that can do this in
just a few chips. What can you suggest?

The sine waves will be used to drive LEDs that illuminate optrodes..
It is expected there will be a small amount of light crosstalking
into the other channels. The crosstalk will be eliminated by FFT on
the output of the photodiode's TIA. Maximum suppression of
crosstalk will happen when the channel frequencies are a multiple
of 1/T where T is the length of time the transform is done over. T
can be 100 ms, 200 ms, 500 ms or 1 s.

I suggest that you ditch the idea of doing it with a switched
capacitor filters and frequency synthesis, and instead do it by
direct digital synthesis and some ADCs.  One reasonably fast
microprocessor (32-bit ARM Cortex) should be able to handle six
channels with ease.

--
Tim Wescott
Control system and signal processing
consultingwww.wescottdesign.com-Hidequoted text -

- Show quoted text -

I've only used a switched cap filters once.  LTC1063.  There were (what
we called) intermodulation distortion at the ~45-50dB level.  It took a
while to identify the SCF as the source.

Switched cap filters sound so nice 'in theory'.

To the spflanze; why so low frequencies?  Wouldn't it be easier to work
up at maybe the 10kHz range... and put 1kHz (or so) between channels?
And then forget about the harmonics.  Or one nice analog low pass after
the photodiodes to kill them all.

George H.

The frequencies are chosen where I expect the noise in the system to be
lowest. This is above the TIA's 1/f noise corner and beneath the zero
created by the capacitance around the TIA's inverting input and feedback
resistor. The frequencies of the six channels are not the same because I
am expecting a little bit of the LED light to crosstalk between
channels. All six optrode chemistries are on the same glass slide.

The six frequencies must be close together because they must all fit
between the 1/f noise corner and the zero. If I use a divide by N
counter, choose only those output frequencies that evenly divide into
the reference frequency, have a large enough input reference frequency,
and enough bits in the the counter, I will have enough frequency
choices.

I am not using a DDS because of the quantization noise. If I use a DDS
with a 10 bit DAC its quantization noise will dominate. It is white
noise that will appear within the bandwidth of the FFT so there is no
filtering it out. I would be using a 16bit AD7606 without the benefit of
its 16bit quantization noise. The quantization noise calculation I have
done shows fewer bits will cause quantization noise to dominate. I do
not know a 16 bit DDS chip. Available 14 bit DDS chips consume too much
power.

My opinion on whether the quantization noise output by a DDS is white or
not has changed a few times. After looking at the figure 20.3b on pdf
page 4 of:
http://oldweb.mit.bme.hu/books/quantization/spectrum.pdf(I have
recently gotten a copy of this book have have yet to fully read it.)
and also reading the conclusion at:
http://www.dsplog.com/2007/03/19/signal-to-quantization-noise-in-

quantized-sinusoidal/

I believe the white noise approximation holds. And I believe this is
most especially true if the DDS tuning word is such that the phase the
sine wave cycle starts at changes from cycle to cycle. This is most of
the time. The exception being when the tuning word divides evenly into
2^N where N is the bit size of the tuning word register and adder.

I am also wondering if I should just square wave modulate the LED light
and count on the FFT to extract the fundamental. So for the first
version of this system I am going to include an analog switch that can
bypass the filtering.

So generate a signal from a micro, and feed it to a DAC with the
precision of your choice.  When I said it would be easy for the
processor, I meant it would be easy _without_ using a dedicated DDS chip.

You can even dither the signal in such a way that the quantization noise
turns blue and is thus easy to filter out.

Note that if there's cross-talk and if you really need 96dB of dynamic
range (as indicated by your proposed use of 16-bit ADCs), you probably
want to choose signal frequencies that not only fit, but whose harmonics
don't fall on one another.  You're almost certainly going to get
distortion; you wouldn't want your 5th harmonic from one light landing
right on the fundamental of another.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Softwarehttp://www.wescottdesign.com

On Thu, 26 Jan 2012 16:32:30 -0800 (PST), Bill Sloman
bill.sloman_at_ieee.org> wrote:

On Jan 27, 12:03 am, spflanze <art...@wavenet.org> wrote:
On Jan 26, 1:36 pm, Bill Sloman <bill.slo...@ieee.org> wrote:









On Jan 26, 7:55 pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:

On 26 Jan., 18:52, Bill Sloman <bill.slo...@ieee.org> wrote:

On Jan 26, 4:19 pm, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 26 Jan 2012 04:54:01 -0800 (PST), Bill Sloman

bill.slo...@ieee.org> wrote:
On Jan 26, 6:46 am, spflanze <art...@wavenet.org> wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the
programmable logic of your choice.

--
Bill Sloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

From a battery? At least with programmable logic, every switching
event is one that you have programmed.

--
Bill Sloman, Nijmegen

If the timers on the processor can do the job it will greatly reduce
the number of counter chips I have on the board. Its clock rate is
much slower than the Blackfin but the FPU might make up for that. I am
looking at it.

Use a single - big-enough - programmable logic device and bury all
your counters (and the rest of the logic) inside it.

I've got a weakness for the Xilinx CoolRunner parts - they don't draw
much current at all. I've never actually been able to use one - not
for want of trying (I've got 15 of then in my desk drawer) - but they
look good.

http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

---
"Not for want of trying"???

The parts languish, according to you, in your desk drawer, and you've
done nothing with them, and justify your sloth, how?

I have decided to abandon the switched capacitor filter and try your
suggestion to use DACs that are constantly updated by the processor. The
Blackfin's clock speed is 600MHz which I expect would be enough to keep
the DAC's updated and do FFT in real time on 12 channels ( 6 signal plus
6 LED monitor ).

My current DAC choice:
http://www.analog.com/en/digital-to-analog-converters/da-converters/
ad5547/products/product.html

I will update the DACs at the same rate as the ADC (200ksps). The DAC
and ADC being correlated in time brings up the interesting question of
what quantization noise will be contributed by the DAC. The correlated
means the square root of the sum of the squares does not apply. Since
the DAC's full scale will always be in use its effective resolution
would a little bit greater than the ADC. One might consider the DAC
won't add any quantization noise. And what would this mean for the
benefit of having a reconstruction filter? Maybe none.

On Thu, 26 Jan 2012 16:32:30 -0800 (PST),BillSloman









bill.slo...@ieee.org> wrote:
On Jan 27, 12:03 am, spflanze <art...@wavenet.org> wrote:
On Jan 26, 1:36 pm,BillSloman<bill.slo...@ieee.org> wrote:

On Jan 26, 7:55 pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:

On 26 Jan., 18:52,BillSloman<bill.slo...@ieee.org> wrote:

On Jan 26, 4:19 pm, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 26 Jan 2012 04:54:01 -0800 (PST),BillSloman

bill.slo...@ieee.org> wrote:
On Jan 26, 6:46 am, spflanze <art...@wavenet.org> wrote:
I need to design a sine wave synthesizer for six channels. Each
channel must have a different frequency and be an exact multiple of
1Hz. Frequency ranges are from 100Hz to 1Khz.

Presumably this means spacing them by about 180Hz - 100Hz, 280Hz ...
820Hz, 1kHz.

If you started off with a 64kHz oscillator, you'd divide that by 640
to get 100Hz, 256 to get 250Hz, by 128 to get 500Hz, by 100 to get
640Hz, by 80 to get 800Hz, and by 64 to get 1kHz - which would all fit
inside  a single programmable logic device.

If you want eight 167 times faster clocks for the switched capacitor
filters, you could multiply 64kHz by 167 giving you a clock frequency
of 10.688MHz, which is pretty much the ideal crystal frequency, and
complicate your programmable logic device appropriately.

With a higher starting frequency you could get more evenly spaced
modulation frequencies that were exact multiples of 1Hz. The
programmable logic device would start drawing lots of current if you
did.

Not enough to make it warm. Modern FPGAs and CPLDs can do a lot of
logic at a 50 MHz clock for a few mA of Icc.

This thing is supposed to be battery operated.

Actually, a more rational choice of frequencies is based on 10^1/6,
1.47

which gives you the series 100Hz, 147Hz, 215Hz, 317Hz, 466Hz, 681Hz
and 1kHz which doesn't lend itself to dividing down from a single
clock, since 147 and 317 are prime numbers.

The 6-bit SN7497 binary rate multiplier could cope with this sort of
problem - it did generate an irregular pulse train, so you had to
follow it with a regular divider that reduces the pulse rate by 2^6 to
smooth out the variations.

2^6 is 64, so if we started with a 81.92kHz clock, set the binary rate
multiplier to 50, then divide by 64, we'd get out 1kHz, while 34,
would give us 680Hz, 23 would give us 460Hz, 16 would give us 320Hz,
11 would give us 220Hz and, 7 would give 140Hz and 5 would give us
100Hz - close enough for government work.

Getting the 167-fold higher frequencies for the switched capacitor
filters means duplicating the logic from a 13.68064MHz clock, which is
entirely practical.

You can obviously duplicate the internal logic of 7497 inside the
programmable logic of your choice.

--
BillSloman, Nijmegen

instead of messing with a bunch of logic, use something like an
stm32f4xx
cortex ARM with lots of timers, capable of running at +100MHz

From a battery? At least with programmable logic, every switching
event is one that you have programmed.

--
BillSloman, Nijmegen

If the timers on the processor can do the job it will greatly reduce
the number of counter chips I have on the board. Its clock rate is
much slower than the Blackfin but the FPU might make up for that. I am
looking at it.

Use a single - big-enough - programmable logic device and bury all
your counters (and the rest of the logic) inside it.

I've got a weakness for the Xilinx CoolRunner parts - they don't draw
much current at all. I've never actually been able to use one - not
for want of trying (I've got 15 of then in my desk drawer) - but they
look good.

http://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

---
"Not for want of trying"???

The parts languish, according to you, in your desk drawer, and you've
done nothing with them, and justify your sloth, how?

On Thu, 26 Jan 2012 16:45:17 -0800, spflanze wrote:
I have decided to abandon the switched capacitor filter and try your
suggestion to use DACs that are constantly updated by the processor. The
Blackfin's clock speed is 600MHz which I expect would be enough to keep
the DAC's updated and do FFT in real time on 12 channels ( 6 signal plus
6 LED monitor ).

My current DAC choice:
http://www.analog.com/en/digital-to-analog-converters/da-converters/

ad5547/products/product.html



I will update the DACs at the same rate as the ADC (200ksps). The DAC
and ADC being correlated in time brings up the interesting question of
what quantization noise will be contributed by the DAC. The correlated
means the square root of the sum of the squares does not apply. Since
the DAC's full scale will always be in use its effective resolution
would a little bit greater than the ADC. One might consider the DAC
won't add any quantization noise. And what would this mean for the
benefit of having a reconstruction filter? Maybe none.

I failed to put two and two together earlier.

By the time you get up to 16-bit ADCs being sampled at 200ksps, your
quantization noise is being swamped by random noise in the ADC.  This
action whitens the ADC quantization noise, so you can treat it as more
random noise, to be filtered out with your FFT process.

As far as the DAC noise goes, it'll still be there, and it'll still be
correlated to the same degree.  It shouldn't cause in-channel problems,
but it may cause some slight harmonic "bleeding".

You can, of course, dither the DAC to whiten the quantization noise:http://eetimes.com/design/embedded/4006431/Sigma-delta-techniques-ext...
DAC-resolution

On Jan 27, 7:04 am, Tim Wescott <t...@seemywebsite.please> wrote:









On Thu, 26 Jan 2012 16:45:17 -0800, spflanze wrote:
I have decided to abandon the switched capacitor filter and try your
suggestion to use DACs that are constantly updated by the processor. The
Blackfin's clock speed is 600MHz which I expect would be enough to keep
the DAC's updated and do FFT in real time on 12 channels ( 6 signal plus
6 LED monitor ).

My current DAC choice:
http://www.analog.com/en/digital-to-analog-converters/da-converters/

ad5547/products/product.html

I will update the DACs at the same rate as the ADC (200ksps). The DAC
and ADC being correlated in time brings up the interesting question of
what quantization noise will be contributed by the DAC. The correlated
means the square root of the sum of the squares does not apply. Since
the DAC's full scale will always be in use its effective resolution
would a little bit greater than the ADC. One might consider the DAC
won't add any quantization noise. And what would this mean for the
benefit of having a reconstruction filter? Maybe none.

I failed to put two and two together earlier.

By the time you get up to 16-bit ADCs being sampled at 200ksps, your
quantization noise is being swamped by random noise in the ADC.  This
action whitens the ADC quantization noise, so you can treat it as more
random noise, to be filtered out with your FFT process.

As far as the DAC noise goes, it'll still be there, and it'll still be
correlated to the same degree.  It shouldn't cause in-channel problems,
but it may cause some slight harmonic "bleeding".

You can, of course, dither the DAC to whiten the quantization noise:http://eetimes.com/design/embedded/4006431/Sigma-delta-techniques-ext...
DAC-resolution

Dithering theory for conventional DACs lays some emphasis on the
probability distribution of the dithering signal - which should
ideally be triangular.

Comment on “Noise averaging and measurement resolution”[Rev. Sci.
Instrum.[bold 70], 2038–2040 (1999)]
AW Sloman - Review of Scientific Instruments, 1999.

lists a few references, including an impressive paper by R M Gray and
T G Stockman, IEEE Trans. Inf. Theory IT-39, 805 (1993)on what goes
wrong if you use a dithering signal with the wrong probability
distribution.

--
Bill Sloman, Nijmegen

On Jan 27, 12:53 am, Bill Sloman <bill.slo...@ieee.org> wrote:









On Jan 27, 7:04 am, Tim Wescott <t...@seemywebsite.please> wrote:

On Thu, 26 Jan 2012 16:45:17 -0800, spflanze wrote:
I have decided to abandon the switched capacitor filter and try your
suggestion to use DACs that are constantly updated by the processor.. The
Blackfin's clock speed is 600MHz which I expect would be enough to keep
the DAC's updated and do FFT in real time on 12 channels ( 6 signal plus
6 LED monitor ).

My current DAC choice:
http://www.analog.com/en/digital-to-analog-converters/da-converters/

ad5547/products/product.html

I will update the DACs at the same rate as the ADC (200ksps). The DAC
and ADC being correlated in time brings up the interesting question of
what quantization noise will be contributed by the DAC. The correlated
means the square root of the sum of the squares does not apply. Since
the DAC's full scale will always be in use its effective resolution
would a little bit greater than the ADC. One might consider the DAC
won't add any quantization noise. And what would this mean for the
benefit of having a reconstruction filter? Maybe none.

I failed to put two and two together earlier.

By the time you get up to 16-bit ADCs being sampled at 200ksps, your
quantization noise is being swamped by random noise in the ADC.  This
action whitens the ADC quantization noise, so you can treat it as more
random noise, to be filtered out with your FFT process.

As far as the DAC noise goes, it'll still be there, and it'll still be
correlated to the same degree.  It shouldn't cause in-channel problems,
but it may cause some slight harmonic "bleeding".

You can, of course, dither the DAC to whiten the quantization noise:http://eetimes.com/design/embedded/4006431/Sigma-delta-techniques-ext...
DAC-resolution

Dithering theory for conventional DACs lays some emphasis on the
probability distribution of the dithering signal - which should
ideally be triangular.

Comment on “Noise averaging and measurement resolution”[Rev. Sci.
Instrum.[bold 70], 2038–2040 (1999)]
AW Sloman - Review of Scientific Instruments, 1999.

lists a few references, including an impressive paper by R M Gray and
T G Stockman, IEEE Trans. Inf. Theory IT-39, 805 (1993)on what goes
wrong if you use a dithering signal with the wrong probability
distribution.

--
Bill Sloman, Nijmegen

Added dithering will not be necessary for what I am doing. The number
of A to D bits was chosen so the voltage value of an LSB is well under
the system noise I am expecting. This is thermal noise from resistors,
equivalent input voltage and current noise from op amps, etc. That
noise will dither for me.