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Guest

Wed Sep 29, 2004 1:37 pm   



message unavailable

Allan Herriman
Guest

Wed Sep 29, 2004 1:37 pm   



On 29 Sep 2004 07:06:36 -0700, ALuPin_at_web.de (ALuPin) wrote:

[snip]
Quote:
Then I changed "rising_edge(Clk)" back to "Clk'event and Clk='1'" and
I got the same result as in the original design.

So why is there a difference at all?

http://groups.google.com/groups?selm=3d63466b.185967697%40netnews.agilent.com

Regards,
Allan

Paul Leventis
Guest

Wed Sep 29, 2004 1:37 pm   



Hi Martin,

Finally got an answer for you on this. This is indeed a bug in the Quartus
extractors; your test case was helpful in tracking down this problem.
Apparently the extractor guys had been looking for a problem like this but
hadn't been able to isolate it until now. A Software Problem Report has
been filed and this should be addressed in a future version of Quartus or a
service pack.

Regards,

Paul Leventis
Altera Corp.

"Martin Schoeberl" <martin.schoeberl_at_chello.at> wrote in message
news:6GGIa.34485$RM6.474195_at_news.chello.at...
Quote:
Since Leonardo is not longer available from Altera I'm trying to use
Quartus
for synthesis. But I get a different output with Quartus. I tracked the
problem down and now my qustion is: Is it a bug or sloopy written VHDL?

The problem is setting output to tristate. See following VHDL code: I
asumed
that it is ok when the databus (d) is set to 'Z' in state 'idl' and this
will not change when changing state to 'rd1'. This was ok with Leonardo.
But
with Quartus I have to set d to 'Z' again in every state. What is the
correct VHDL code?

Martin

process(clk, reset, din, mem_wr_addr, mem_rd, mem_wr)
begin
if (reset='1') then
state <= idl;
a <= "ZZZZZZZZZZZZZZZZZZZ";
d <= "ZZZZZZZZ";
....
elsif rising_edge(clk) then
case state is
when idl =
a <= "ZZZZZZZZZZZZZZZZZZZ";
d <= "ZZZZZZZZ";

if (mem_rd='1') then
a <= din(16 downto 0) & "00";
nram_cs <= '0';
ram_access <= '1';
i := ram_cnt;
nrd <= '0';
state <= rd1;
elsif (mem_wr='1') then
...
when rd1 =
d <= "ZZZZZZZZ"; -- this line is necessary in Quartus but
NOT in Leonardo
i := i-1;
if (i=0) then
state <= rd2;
mem_din(7 downto 0) <= d;
a(1 downto 0) <= "01";
i := ram_cnt;
end if;

when rd2 =
d <= "ZZZZZZZZ"; -- same as in rd1
i := i-1;
if (i=0) then
...

--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/



Ajeetha Kumari
Guest

Wed Sep 29, 2004 1:37 pm   



Hi,
Have a look at Ben Cohen's book. That's my choice. Please visit
http://www.vhdlcohen.com

HTH,
Ajeetha

http://www.noveldv.com


vhdl_uk_at_yahoo.co.uk (MACEI'S) wrote in message news:<fdfcada5.0307081038.6f1c5d22_at_posting.google.com>...
Quote:
Can anyone tell me good books or web sites related to following.
1. MAKE file for VHDL ( XILINX)
2. Implementation of Coding using FPGA

Rgds

MACIE


Isaac
Guest

Wed Sep 29, 2004 1:37 pm   



Sorry , I changes my code to Input .......
So please read SR_DATA_IO_int (13 downto 0) as Input (13 downto 0)

Cheers

Isaac


Allan Herriman <allan_herriman.hates.spam_at_agilent.com> wrote in message news:<0ccqgvs49b23uhvhb8g5j2hbfeika71kui_at_4ax.com>...
Quote:
On 9 Jul 2003 11:00:32 -0700, fpga_uk_at_yahoo.co.uk (Isaac) wrote:

Yes ALLAN I am Sure I am using different bits


E.g

This VHDL code I tried but in PAR file no pin assignment for signal 13 to 7

process(CLK_2X,SR_ADDR_IO_int,SR_DATA_IO_int,SR_IRD_int,SR_IWR_int,SR_IVCS_V3_int)
begin
if RISING_EDGE(CLK_2X) then
if SR_IVCS_V3_int = '0' then
if SR_IWR_int = '0' then
if SR_ADDR_IO_int = "001100" then
LED_V3_int <= SR_DATA_IO_int(13 downto 7);
end if;
end if;
end if;
end if;
end process P_SRAM2LED;


It's hard to say exactly what's going on, because you didn't include
the right bits of VHDL (i.e. the signal declarations).
Which signal is related to the "INPUT" signal in your first post?

The only signal is likely to be of type std_logic_vector is
SR_ADDR_IO_int, and that is only six bits long. Hmmm, the error
messages indicated that the six least signficant bits of INPUT were
used.
Do you have an assignment like:
SR_ADDR_IO_int <= INPUT(5 downto 0);
anywhere in your code?

You also might want to fix the sensitivity list.

Regards,
Allan.


Mike Treseler
Guest

Wed Sep 29, 2004 1:37 pm   



Alan Fitch wrote:

Quote:

I personally don't think it should be a warning, as it's quite legal
to declare null vectors

I agree.

A bad assignment to a null vector will cause other errors.
A null vector declaration alone is innocuous.

If one bit is 0 to 0 then
no bits must be 0 to -1

Let's see:
-------------------

entity null_string is
end null_string;

architecture sim of null_string
is
constant null_vec : std_logic_vector := "";
constant one_vec : std_logic_vector := "0";
constant two_vec : std_logic_vector := "00";

begin

what : process is
begin
report "null_vec is "& integer'image(null_vec'left)
& " to "& integer'image(null_vec'right);
report " one_vec is "& integer'image( one_vec'left)
& " to "& integer'image( one_vec'right);
report " two_vec is "& integer'image( two_vec'left)
& " to "& integer'image( two_vec'right);
wait;
end process what;

end sim;

--VSIM 1> run
--# ** Note: null_vec is 0 to -1
--# ** Note: one_vec is 0 to 0
--# ** Note: two_vec is 0 to 1

------------------------

I suppose that null vectors are rare as signals
but null vector constants and variables are necessary to make
clean vector functions.


--Mike Treseler

Clyde R. Shappee
Guest

Wed Sep 29, 2004 1:37 pm   



Hi, Mike,

Could please enlighten me on your usage

integer'image(null_vec'left)

What's it doing? Is image the function that Ben Cohen provides on his CD
with his books?

What is integer' doing? type casting?

Have I been asleep, or why don't I know about this from all of my reading.

Please advise, and thank you.

Clyde

Mike Treseler wrote:

Quote:
Alan Fitch wrote:


I personally don't think it should be a warning, as it's quite legal
to declare null vectors

I agree.

A bad assignment to a null vector will cause other errors.
A null vector declaration alone is innocuous.

If one bit is 0 to 0 then
no bits must be 0 to -1

Let's see:
-------------------

entity null_string is
end null_string;

architecture sim of null_string
is
constant null_vec : std_logic_vector := "";
constant one_vec : std_logic_vector := "0";
constant two_vec : std_logic_vector := "00";

begin

what : process is
begin
report "null_vec is "& integer'image(null_vec'left)
& " to "& integer'image(null_vec'right);
report " one_vec is "& integer'image( one_vec'left)
& " to "& integer'image( one_vec'right);
report " two_vec is "& integer'image( two_vec'left)
& " to "& integer'image( two_vec'right);
wait;
end process what;

end sim;

--VSIM 1> run
--# ** Note: null_vec is 0 to -1
--# ** Note: one_vec is 0 to 0
--# ** Note: two_vec is 0 to 1

------------------------

I suppose that null vectors are rare as signals
but null vector constants and variables are necessary to make
clean vector functions.

--Mike Treseler


Clyde R. Shappee
Guest

Wed Sep 29, 2004 1:37 pm   



Thanks...

I guess there are features in VHDL 93 that I have not been aware of. I'll have
to read up and give them a try.

CRS

Mike Treseler wrote:

Quote:
Clyde R. Shappee wrote:
Hi, Mike,

Could please enlighten me on your usage

integer'image(null_vec'left)

It an integer, the left index of the vector.

What's it doing? Is image the function that Ben Cohen provides on his CD
with his books?

No. Standard VHDL. Supported by all the sim and synth tools I have tried.

What is integer' doing? type casting?

No. It's a built in VHDL "attribute" , a kind of function.

Have I been asleep, or why don't I know about this from all of my reading.

A lot of the cool parts of VHDL-93 were neglected, because
they didn't work with every version of every tool.
They now work with most versions of most tools, so
feel free to use them.

-- Mike Treseler


a
Guest

Wed Sep 29, 2004 1:37 pm   



adarsh arora escribió:
Quote:
can u tell me from where i will get free downloadable softwares for
VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with
free licences.
waiting for ur help
http://ghdl.free.fr


Ray Andraka
Guest

Wed Sep 29, 2004 1:37 pm   



Yes, we have. One approach we had success with was one that used a DDS type
setup where the increment value got bumped up/down depending on the phase of the
accumulator vs the reference. Works quite well as long as the reference is
fairly stable. In our case we needed to track a mechanical system which had a
fairly high variance on the reference, so we wound up putting a lot of extra
crap on the design to improve the transient response without it going into
oscillation. Still lots smaller than doing a digital equivalent of an analog
PLL though.

Jason Berringer wrote:

Quote:
Hello guru's

I was wondering if anyone has ever attempted a phase lock loop in digital
before (specifically VHDL). I'm looking for some examples or pointers on
trying to build one for a low frequency range of 200 Hz to 200 kHz. I would
appreciate any comments or suggestions. Google didn't get me very far, so if
you know of any app notes, etc. please let me know.

Thanks,

Jason

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray_at_andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

Kevin Neilson
Guest

Wed Sep 29, 2004 1:37 pm   



My all-digital PLL was similar and worked very well. My reference clock and
system clock were pretty stable so I didn't do a lot of analysis. I just
designed the loop with a small gain, so it took a bit to lock on (which
wasn't a problem in my application) but once it was locked it was very
stable and didn't oscillate. The only problem with the low gain is that it
took forever to lock in the simulation, so I made an adjustable loop gain so
I could kick it up for simulations and see it lock faster (although it rung
a bit before locking.)
-Kevin

"Ray Andraka" <ray_at_andraka.com> wrote in message
news:3F131077.9C3A8039_at_andraka.com...
Quote:
Yes, we have. One approach we had success with was one that used a DDS
type
setup where the increment value got bumped up/down depending on the phase
of the
accumulator vs the reference. Works quite well as long as the reference
is
fairly stable. In our case we needed to track a mechanical system which
had a
fairly high variance on the reference, so we wound up putting a lot of
extra
crap on the design to improve the transient response without it going into
oscillation. Still lots smaller than doing a digital equivalent of an
analog
PLL though.

Jason Berringer wrote:

Hello guru's

I was wondering if anyone has ever attempted a phase lock loop in
digital
before (specifically VHDL). I'm looking for some examples or pointers on
trying to build one for a low frequency range of 200 Hz to 200 kHz. I
would
appreciate any comments or suggestions. Google didn't get me very far,
so if
you know of any app notes, etc. please let me know.

Thanks,

Jason

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray_at_andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759



Ray Andraka
Guest

Wed Sep 29, 2004 1:37 pm   



Mine used a barrel shift in the feedback to get a gain that increased with the
size of the error. Had to do that to get a quick lock and still be able to
chase the reference. The reference was derived from a quad encoder on the
mechanical media path. The PLL had to adjust a process to keep a certain number
of events between encoder pulses. All in all, it was a pretty nasty problem
because of the dynamics and limited resolution of the encoder.

Kevin Neilson wrote:

Quote:
My all-digital PLL was similar and worked very well. My reference clock and
system clock were pretty stable so I didn't do a lot of analysis. I just
designed the loop with a small gain, so it took a bit to lock on (which
wasn't a problem in my application) but once it was locked it was very
stable and didn't oscillate. The only problem with the low gain is that it
took forever to lock in the simulation, so I made an adjustable loop gain so
I could kick it up for simulations and see it lock faster (although it rung
a bit before locking.)
-Kevin

"Ray Andraka" <ray_at_andraka.com> wrote in message
news:3F131077.9C3A8039_at_andraka.com...
Yes, we have. One approach we had success with was one that used a DDS
type
setup where the increment value got bumped up/down depending on the phase
of the
accumulator vs the reference. Works quite well as long as the reference
is
fairly stable. In our case we needed to track a mechanical system which
had a
fairly high variance on the reference, so we wound up putting a lot of
extra
crap on the design to improve the transient response without it going into
oscillation. Still lots smaller than doing a digital equivalent of an
analog
PLL though.

Jason Berringer wrote:

Hello guru's

I was wondering if anyone has ever attempted a phase lock loop in
digital
before (specifically VHDL). I'm looking for some examples or pointers on
trying to build one for a low frequency range of 200 Hz to 200 kHz. I
would
appreciate any comments or suggestions. Google didn't get me very far,
so if
you know of any app notes, etc. please let me know.

Thanks,

Jason

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray_at_andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759



--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray_at_andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

Ajeetha Kumari
Guest

Wed Sep 29, 2004 1:37 pm   



Hi,
Please check VHDL FAQ. Xilinix Webpack with Modelsim, SympanyEDA are few to name.

HTH,
Ajeetha
http://www.noveldv.com

a <a_at_a.com> wrote in message news:<beukeb$aql1_at_noticias.madritel.es>...
Quote:
adarsh arora escribió:
can u tell me from where i will get free downloadable softwares for
VHDL/verilog simulation and synthesis , SPICE ,IC Station...... with
free licences.
waiting for ur help
http://ghdl.free.fr


Mike Treseler
Guest

Wed Sep 29, 2004 1:37 pm   



Thomas Stanka wrote:
Quote:
Mike Treseler <mike.treseler_at_flukenetworks.com> wrote:

If I have constants and functions to share between processes,
I use the default "work" library, as this is much less trouble
and more portable than naming and maintaining my own library.


I don't think that this is very portable. If you reuse your code, you
have to be very careful about constant names, there might be more
packages including a constant with a specific name. Eg. you use a
library bus_master and a library bus_slave, you don't have to care
about constants names with the same name for master and slave IP.

Yes, there could be name conflicts, but this
would be discovered at compile time and is easily
corrected in the source file being edited.

The upside is that all the developers can CVS to/from
a single directory and compile with a very simple make procedure.

I agree that this scheme might become difficult
for a large number of developers.


-- Mike Treseler

Kevin Neilson
Guest

Wed Sep 29, 2004 1:37 pm   



"Ray Andraka" <ray_at_andraka.com> wrote in message
news:3F134720.D19A8BCA_at_andraka.com...
Quote:
Mine used a barrel shift in the feedback to get a gain that increased with
the
size of the error. Had to do that to get a quick lock and still be able
to
chase the reference. The reference was derived from a quad encoder on the
mechanical media path. The PLL had to adjust a process to keep a certain
number
of events between encoder pulses. All in all, it was a pretty nasty
problem
because of the dynamics and limited resolution of the encoder.

Kevin Neilson wrote:


I like that idea. Actually, I recalled that mine had a time-varying gain,
but it was much simpler. The gain was high before lock, and after locking,
the gain switched to something lower. The gain was just implemented by
left-shifting the output from the loop filter (which was just a comb or
moving-average filter), so the gain could only be powers of two. Does the
barrel shifter you describe increase the order of the loop? That probably
makes it a lot harder to describe mathematically. I would have liked to do
an analysis of mine, but of course I didn't have time, and for my
application stability was much more important than lock time so I didn't
really have to optimize it.
-Kevin

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