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Mike Treseler
Guest
Wed Sep 29, 2004 1:37 pm
rickman wrote:
Quote:
. . .
differently and reaches the end of the process. At the top of this
process, it waits for the "Start" signal again, but if the "Start" flag
is already set, it hangs.
So does a wait statement always perform an edge detect by default?
No.
You can wait UNTIL an expression has a value of true or
you can wait ON a signal_id for *any* value change.
Quote:
Here is my wait statement...
wait until ARM_Bus_Start or rising_edge(Reset);
If ARM_Bus_Start is already set when this executes, the process hangs
here.
Consider View, Source
and setting some breakpoints.
Run/step code and watch the signals.
Either the wait is in a different process
or ARM_Bus_Start is not true at the right time.
-- Mike Treseler
rickman
Guest
Wed Sep 29, 2004 1:37 pm
Mike Treseler wrote:
Quote:
rickman wrote:
. . .
differently and reaches the end of the process. At the top of this
process, it waits for the "Start" signal again, but if the "Start" flag
is already set, it hangs.
So does a wait statement always perform an edge detect by default?
No.
You can wait UNTIL an expression has a value of true or
you can wait ON a signal_id for *any* value change.
Here is my wait statement...
wait until ARM_Bus_Start or rising_edge(Reset);
If ARM_Bus_Start is already set when this executes, the process hangs
here.
Consider View, Source
and setting some breakpoints.
Run/step code and watch the signals.
Either the wait is in a different process
or ARM_Bus_Start is not true at the right time.
I did look at everything in detail in the simulator. The wait statement
shown above executes with ARM_Bus_Start set to true and the process is
hung at that wait. I have solved the problem by testing ARM_Bus_Start
before I execute the wait and it runs as expected. So it is pretty
clear that the issue is the wait requiring a change in state of a signal
in the expression before it evaluates the expression.
I will try some more tests when I get a chance.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL
http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Rienk van der Scheer
Guest
Wed Sep 29, 2004 1:37 pm
rickman wrote:
Quote:
Here is my wait statement...
wait until ARM_Bus_Start or rising_edge(Reset);
If ARM_Bus_Start is already set when this executes, the process hangs
here.
I am using ModelSim XE II/Starter 5.6e.
Suggestion:
if (ARM_Bus_Start) then
-- continue immediately
else
-- note: removed rising_edge because it is implied in the 'wait until'
wait until ARM_Bus_Start or Reset;
endif;
Your problem is that you should remember that a wait statement in VHDL
will always wait for some event. In your situation, you don't want to
wait at all when the condition is already met.
Regards,
Rienk
Alan Fitch
Guest
Wed Sep 29, 2004 1:37 pm
"Thomas Stanka" <thomas_at_stanka-web.de> wrote in message
news:d92cdee8.0308040057.30784b34_at_posting.google.com...
Quote:
Mike Treseler <mike.treseler_at_flukenetworks.com> wrote:
You can wait UNTIL an expression has a value of true or
you can wait ON a signal_id for *any* value change.
Modelsim don't come along with
mysig<='1';
wait for 1 us;-- to allow signal update
wait until mysig='1';
because mysig is allready '1'. In my opinion this is a bug, Modelsim
should perform a test if mysig is allready '1' (Maybe there's
someone
out correcting my opinion).
No, it's not a bug. It's the way VHDL is defined. As someone else
said, a wait statement is implicitly sensitive to all the signals
in the boolean condition. So in your example, you can re-write
wait until mysig = '1';
as
wait on mysig until mysig = '1';
In Rick's original example, where the testbench "hung", you can
sometimes use this approach
wait until ArmStart for 100 us; -- 100 us timeout
if ArmStart'EVENT then
-- yippee, event occurred before time out
-- so carry on
else
report "ArmStart didn't occur within 100 us - Doh!";
end if;
regards
Alan
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
FE
Guest
Wed Sep 29, 2004 1:37 pm
Don't waste your time. Think 2 sec. If the wait until was sensitive on
condition level and your signal ARM_Bus_Start is true for 10ns and your
simulator's resolution is set at 1ps then the process would be executed
10000 times in row. Your simulation will take 6 month to execute.
Check in your vhdl book. If you don't have a book, I recommend The
Designer's Guide to VHDL by Peter Ashenden.
P.A. wrote in is book : the condition is tested whenever an event occurs on
any of the signals mentioned in the condition.
regards
FE
Sr ASIC Designer
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F2DF114.F6DDB8AE_at_yahoo.com...
Quote:
Mike Treseler wrote:
rickman wrote:
. . .
differently and reaches the end of the process. At the top of this
process, it waits for the "Start" signal again, but if the "Start"
flag
is already set, it hangs.
So does a wait statement always perform an edge detect by default?
No.
You can wait UNTIL an expression has a value of true or
you can wait ON a signal_id for *any* value change.
Here is my wait statement...
wait until ARM_Bus_Start or rising_edge(Reset);
If ARM_Bus_Start is already set when this executes, the process hangs
here.
Consider View, Source
and setting some breakpoints.
Run/step code and watch the signals.
Either the wait is in a different process
or ARM_Bus_Start is not true at the right time.
I did look at everything in detail in the simulator. The wait statement
shown above executes with ARM_Bus_Start set to true and the process is
hung at that wait. I have solved the problem by testing ARM_Bus_Start
before I execute the wait and it runs as expected. So it is pretty
clear that the issue is the wait requiring a change in state of a signal
in the expression before it evaluates the expression.
I will try some more tests when I get a chance.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL
http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Alan Fitch
Guest
Wed Sep 29, 2004 1:37 pm
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F2EFF97.9072E30A_at_yahoo.com...
Quote:
I added a variable to calculate a time for a wait statement in a
testbench and am not getting this error from ModelSim...
^^^ now??
Quote:
Signal arm_command is read by the VITAL process but is NOT in the
sensitivity list
This is the line of code producing the error...
WaitTime := (ARM_command.RelTime - (now - CurrentTime));
I follow this up with a check for negative values before using in
the
wait. ARM_command is a signal and WaitTime and CurrentTime are
variables. And of course all these objects are of type time. This
same
calculation done directly in the wait statement gives no error.
It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?
If it's a warning, just ignore it.
If it's an error, it sounds like a bug.
regards
Alan
p.s. I know it's nothing to do with this error, but I'd check for
negative values before assigning, just because I am paranoid (!). In
particular I wonder what happens if you assign a negative time value
to a variable of type time?
e.g.
assert ( (ARM_command.RelTime - (now - CurrentTime)) >= 0 ns )
report "negative time value";
waittime := ...
p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
rickman
Guest
Wed Sep 29, 2004 1:37 pm
Alan Fitch wrote:
Quote:
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F2EFF97.9072E30A_at_yahoo.com...
I added a variable to calculate a time for a wait statement in a
testbench and am not getting this error from ModelSim...
^^^ now??
Yes, now, not "not".
Quote:
Signal arm_command is read by the VITAL process but is NOT in the
sensitivity list
This is the line of code producing the error...
WaitTime := (ARM_command.RelTime - (now - CurrentTime));
I follow this up with a check for negative values before using in
the
wait. ARM_command is a signal and WaitTime and CurrentTime are
variables. And of course all these objects are of type time. This
same
calculation done directly in the wait statement gives no error.
It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?
If it's a warning, just ignore it.
If it's an error, it sounds like a bug.
regards
Alan
p.s. I know it's nothing to do with this error, but I'd check for
negative values before assigning, just because I am paranoid (!). In
particular I wonder what happens if you assign a negative time value
to a variable of type time?
e.g.
assert ( (ARM_command.RelTime - (now - CurrentTime)) >= 0 ns )
report "negative time value";
waittime := ...
p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.
The possibility of being negative was why I was using a variable instead
of just sticking it in the wait statement. I thought it would be better
to calculate it once and then test it and set to zero if negative. So
now I have to do the calculation twice.
I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.
Last_Bus_Action := Bus_Command.Bus_Action;
In both cases, part of the right hand expression is an element in a
record. The error reports the record "Bus_Command" as missing from the
sensitivity list, not the element! Could the VITAL process have a bug
in regards to dealing with record elements? This doesn't sound likely
to me. But then I don't even know what the VITAL process is.
Maybe I need to contact Mentor about ModelSim.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL
http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Alan Fitch
Guest
Wed Sep 29, 2004 1:37 pm
<snip>
Quote:
p.p.s.
Reading the LRM shows I really am being paranoid, as type TIME is
guaranteed to include the range -2**9+1 to 2^9-1, so negative
time values in variables of type TIME are ok.
That should have been -2**31+1 to 2**31-1, sorry.
Quote:
The possibility of being negative was why I was using a variable
instead
of just sticking it in the wait statement. I thought it would be
better
to calculate it once and then test it and set to zero if negative.
So
now I have to do the calculation twice.
OK, sounds sensible.
Quote:
I am getting the same error from a different assignment now. The
common
point is that a signal is on the right hand side of the assignment
and a
variable is on the left. I am using the variable assignment
operator,
":=". This is reported as an error, not a warning.
Last_Bus_Action := Bus_Command.Bus_Action;
In both cases, part of the right hand expression is an element in a
record. The error reports the record "Bus_Command" as missing from
the
sensitivity list, not the element! Could the VITAL process have a
bug
in regards to dealing with record elements? This doesn't sound
likely
to me. But then I don't even know what the VITAL process is.
That is weird. I thought that VITAL was a label you'd used in your
code, e.g.
vital: process...
But if it's not?
If it's vital as in "VITAL - VHDL Initiative Toward Asic Libraries"
then
I'd only expect to see it referred to if you were doing back-annotated
gate level simulation?
Quote:
Maybe I need to contact Mentor about ModelSim.
Sounds like a good idea.
regards
Alan
--
Alan Fitch
Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.
Brian Drummond
Guest
Wed Sep 29, 2004 1:37 pm
On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4_at_yahoo.com>
wrote:
Quote:
Alan Fitch wrote:
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
This is the line of code producing the error...
WaitTime := (ARM_command.RelTime - (now - CurrentTime));
It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?
I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.
Last_Bus_Action := Bus_Command.Bus_Action;
If that's the case, then assigning the record field to an intermediate
signal would probably "fix" it. Not nice, but as an expedient to (a)
keep moving and (b) home in on the real problem, maybe worth trying.
-- parallel signal assignment
tempAction <= Bus_Command.Bus_Action;
-- within process or whatever
Last_Bus_Action := tempAction;
Assuming it works, then a support call to ModelSim, asking why one
works, but not the other, would be very worthwhile.
- Brian
rickman
Guest
Wed Sep 29, 2004 1:37 pm
Brian Drummond wrote:
Quote:
On Tue, 05 Aug 2003 12:18:31 -0400, rickman <spamgoeshere4_at_yahoo.com
wrote:
Alan Fitch wrote:
"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
This is the line of code producing the error...
WaitTime := (ARM_command.RelTime - (now - CurrentTime));
It sounds like Modelsim is confused. Is it actually an error, or just
a warning? Having a signal read that is not in the sensitivity list
is not an error. Can you disable Modelsim's synthesis checks?
I am getting the same error from a different assignment now. The common
point is that a signal is on the right hand side of the assignment and a
variable is on the left. I am using the variable assignment operator,
":=". This is reported as an error, not a warning.
Last_Bus_Action := Bus_Command.Bus_Action;
If that's the case, then assigning the record field to an intermediate
signal would probably "fix" it. Not nice, but as an expedient to (a)
keep moving and (b) home in on the real problem, maybe worth trying.
-- parallel signal assignment
tempAction <= Bus_Command.Bus_Action;
-- within process or whatever
Last_Bus_Action := tempAction;
Assuming it works, then a support call to ModelSim, asking why one
works, but not the other, would be very worthwhile.
- Brian
I already have a work around and have sent the problem to Xilinx (Mentor
does not support the Starter Edition). But thanks.
--
Rick "rickman" Collins
rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL
http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Mike Treseler
Guest
Wed Sep 29, 2004 1:37 pm
Isaac wrote:
Quote:
I am using 12 same entitites using Component decleration method.
Perhaps you mean a top architecture with 12 instances of some entity.
Quote:
I am
giving input to 12 entities in such a way that the internal signal's
in each entity has different values from each other at any time. Now
the top vhdl final in which all the component decleration are defined
, I want to use the internal signal's of each block to perform some
calculation. The probelm is that in each of the 12 entities signal has
the same name (as I am using component decleration method to generate
same entity 12 time).
Each instance has a unique label:
my_entity_1 : entity work.my_entity
port map (reset => reset_sig, -- [in]
clk => clk_sig, -- [in]
i => i_1_sig, -- [in]
o => o_1_sig); -- [out]
my_entity_12 : entity work.my_entity
port map (reset => reset_sig, -- [in]
clk => clk_sig, -- [in]
i => i_12_sig, -- [in]
o => o_12_sig); -- [out]
The signal associated with an instance port is whatever
you define it to be in the port map.
I think of this as "wiring up" the instances.
These "wire" signals must be declared between
the IS and BEGIN of the top architecture.
It can be a different signal for each instance if you like.
Quote:
Is there is any way to access these Signal in VHDL?
These signals are accessible anywhere in the top architecture.
-- Mike Treseler
Ray Andraka
Guest
Wed Sep 29, 2004 1:37 pm
It is pretty straight forward. See my article in XCell about digital
downcoverters. There is a link on the publications page of my website to
the paper.
Jan wrote:
Quote:
Hi,
Can anyone point me at a vhdl design for a DDC, Digital Down Convertor,
in an FPGA. Preferably free.
It should be a wideband design with up to 10MHz and as low as 100KHz
bandwidth. Resolution of adc is 14bits.
Also it should be possible to synthesise it with the Xilinx Webpack.
Thanks for any help
Jan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray_at_andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Clyde R. Shappee
Guest
Wed Sep 29, 2004 1:37 pm
Then, please enlighten us as to how to use the block rams with Web-pack, without
using the core generator.
I looked at your web page and did not see in your example projects how you did
it.
Clyde
Nial Stewart wrote:
Quote:
Clyde R. Shappee <clydes_at_the_world.com> wrote in message
news:3F64ABE0.783CE26F_at_the_world.com...
I just did a little experiment with the webpack software, instantiating a
fifo in the block ram.... and the software black boxes it because it
doesn't
know how to hook it up.
The .edn file from the core generator is missing, and as such XST does
not
know how to configure the block ram.
This is consistent with information I received from the Xilinx Apps guy.
Clyde
What are you trying to instantiate? If it's a component that you
previously generated from Coregen then it won't work as coregen
stitches whatever Blockrams together to get the structure you
need, creates a wrapper round them and gives it a sensible name.
If you try to instantiate the wrapper web-pack won't know what you're
talking about.
Have a look at the data sheet for whatever device you're targeting to
see what the blockrams should be called. As an example a 256* 8 bit dual
port
ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for
port names.
If you want bigger/wider structures than you get with one block ram you've
got to stitch them together yourself (with a wrapper if you want).
It would be almost a complete waste of time for Xilinx to release web-pack
if you couldn't access blockrams.
Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk
Uwe Bonnes
Guest
Wed Sep 29, 2004 1:37 pm
In comp.arch.fpga Clyde R. Shappee <clydes_at_the_world.com> wrote:
: Then, please enlighten us as to how to use the block rams with Web-pack, without
: using the core generator.
: I looked at your web page and did not see in your example projects how you did
: it.
Here is how I instantiate in in some verilog project:
RAMB4_S16_S16 ram0(.DOA(),.DOB(rdo_data_a),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dba_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));
RAMB4_S16_S16 ram1(.DOA(),.DOB(rdo_data_b),.ADDRA(rdo_wfifo_cnt),.ADDRB(rdo_rfifo_cnt),
.CLKA(!mclk_i),.CLKB(rclk),.DIA(dbb_r[15:0]),.DIB(16'b0),
.ENA(1'b1),.ENB(1'b1),
.RSTA(1'b0),.RSTB(1'b0),.WEA(rdo_read_rrrr),.WEB(1'b0));
Hpe this helps.
Bye
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Nial Stewart
Guest
Wed Sep 29, 2004 1:37 pm
Clyde R. Shappee <clydes_at_the_world.com> wrote in message
news:3F6891AD.B0291535_at_the_world.com...
Quote:
Then, please enlighten us as to how to use the block rams with Web-pack,
without
using the core generator.
I already have.
"Have a look at the data sheet for whatever device you're targeting to
see what the blockrams should be called. As an example a 256* 8 bit dual
port ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data
sheet for port names."
And see Uwe's example above/below.
Spoon feeding bit.....
If you look in webpack/vhld/src/unisims/unisim_VCOMP.vhd you'll see
the models for all the rams supported. RAMB4 is supported in Spartan
devices (as specified in the SpartanII-E data sheet), I presume
RAMB16 configurations are supported in Virtex devices.
Quote:
I looked at your web page and did not see in your example projects how you
did
it.
Download pico2spart.zip, unzip it and look at ../SW/picocode.vhd
This contains five blockram instantiations with the associated
configurations
containing the software for the Virtex picoblaze in a SpartanII.
These Blockrams are 1024 addresses* 4 bits.
For an example of a singla 256*16 ram download picoblaze.zip, then look at
.../sw/ROM_form.vhd . This is a template file, but it's exactly the way
the ram's instantiated in a real design.
Did you ask the Xilinx apps guy "Does web-pack support blockrams?", or
"Does web-pack support this ram I've generated with Coregen?" ?.
As I said, it would be almost a complete waste of time for Xilinx to
release web-pack if you couldn't get at the Rams.
Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk
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