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Guest

Fri Mar 04, 2016 10:01 pm   



On Thursday, October 17, 1996 at 12:00:00 AM UTC-7, Edwin Naroska wrote:
Quote:
Hi,

Vasily A.Syngaevsky wrote:

Hi everybody !
Does anybody know where to find free or purchase
VHDL model of 386 or 486 microprocessor ?
Thanks in advance,
Vasily

The following links point to some servers containing "non commercial"
VHDL models. Note, there may be some limitations and restrictions
concerning the use of this software.

MSU:
http://www.erc.msstate.edu/mpl/rassp/modeling/html/modeling.html
Free Modeling Foundation (FMF):
http://vhdl.org/vi/fmf/
The Hamburg VHDL archive:
http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html
RASSP www site:
http://rassp.scra.org/information/public-vhdl/models/models.html
University of Strasbourg:
http://erm1.u-strasbg.fr/db/ or ftp://erm1.u-strasbg.fr/pub/vhdl/
Doulos High Level Design Web site; Monthly-updated Original Models
(developed by Doulos):
http://www.doulos.co.uk/informationresource/index.htm
A pipelined version of the DLX RISC processor (with some restrictions),
by Neil Shipp:
http://www.pads.uwaterloo.ca/~nlshipp/dlx
EDIF LPM - Library of Parameterized Modules:
http://www.edif.org/

Here are some links to commercial model sites.

Viewlogic's on-line CAE/CAD model library information center:
http://www.viewlogic.com/ModelSite/
Virtual Chips, Inc.:
http://www.vchips.com/
3Soft's Web Page:
http://www.3soft.com

For other commercial model vendors see FAQ part 3 products & services at
http://www.vhdl.org/vi/comp.lang.vhdl/

Bye,...
Edwin
--
-----------------------------------------------------------
Edwin Naroska
Computer Engineering Institute
(Lehrstuhl fuer Datenverarbeitungssysteme)
University of Dortmund
44221 Dortmund
Germany

email: edwin_at_ds.e-technik.uni-dortmund.de
phone: ++49 231 7552406
fax: ++49 231 7553251
-----------------------------------------------------------


Heads up- most of your links dont work

KJ
Guest

Fri Mar 04, 2016 10:09 pm   



On Friday, March 4, 2016 at 3:01:23 PM UTC-5, dylan...@gmail.com wrote:
Quote:

Heads up- most of your links dont work


Wow, that's a shocker. Links that were posted 20 years ago don't work. Whooda thunk?


Guest

Sat Nov 19, 2016 6:12 pm   



hi sir,
i am also doing a project in viterbi decoder of convolutional codes in VHDL.
constraint length k=3.code rate=1/2.i am now having some design problems in decoder side so if u have any coding in VHDL ping me at azarudeentheboss_at_gmail.com thank you

Enes Erdin
Guest

Thu Jan 19, 2017 7:06 pm   



On Saturday, November 19, 2016 at 11:12:05 AM UTC-5, azarudee...@gmail.com wrote:
Quote:
hi sir,
i am also doing a project in viterbi decoder of convolutional codes in VHDL.
constraint length k=3.code rate=1/2.i am now having some design problems in decoder side so if u have any coding in VHDL ping me at azarudeentheboss_at_gmail.com thank you


I designed a turbo decoder in VHDL in 2008.


Guest

Mon Jun 19, 2017 1:51 pm   



Dffvv


Guest

Sat Jul 29, 2017 9:08 am   



On Friday, 19 December 2014 05:05:02 UTC+8, Daniel Kho wrote:
Quote:
On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote:
On 05/12/2014 12:48, Anssi Saari wrote:

Is Modelsim still not implementing VHDL 2008? I have some code with the
"new" if ... generate with else branch but Modelsim 10.1e doesn't seem
to support that. Or is it just that the Altera's Starter Edition doesn't
support that? I don't have a Modelsim PE or SE installed right now... I
tried case in generate as well but it didn't work any better.

Modelsim 10.1e was released in June of 2013. Your code compiled OK in
the latest 10.3d release.

Modelsim SE is an obsolete product and replaced by Questa core.

Regards,
Hans
www.ht-lab.com




Example code, vcom -2008 says
** Error: generate_prob.vhdl(20): near "else": syntax error
(line 20 is the else generate line.)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity dummy is
generic (
some_boolean_generic : boolean := false);
port(
clk : in std_logic;
reset_n : in std_logic;
dout : out std_logic
);
end dummy;

architecture dummy_arch of dummy is

begin

some_label: if some_boolean_generic = false generate
dout <= '0';
else generate
dout <= '1';
end generate some_label;

end dummy_arch;


The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website.

-dan


Does VHDL-2008 need to be activated?

Allan Herriman
Guest

Sun Jul 30, 2017 8:13 am   



On Sat, 29 Jul 2017 00:08:40 -0700, sockpemote wrote:

Quote:
On Friday, 19 December 2014 05:05:02 UTC+8, Daniel Kho wrote:
On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote:
On 05/12/2014 12:48, Anssi Saari wrote:

Is Modelsim still not implementing VHDL 2008? I have some code with
the "new" if ... generate with else branch but Modelsim 10.1e
doesn't seem to support that. Or is it just that the Altera's
Starter Edition doesn't support that? I don't have a Modelsim PE or
SE installed right now... I tried case in generate as well but it
didn't work any better.

Modelsim 10.1e was released in June of 2013. Your code compiled OK in
the latest 10.3d release.

Modelsim SE is an obsolete product and replaced by Questa core.

Regards,
Hans www.ht-lab.com




Example code, vcom -2008 says ** Error: generate_prob.vhdl(20):
near "else": syntax error (line 20 is the else generate line.)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity dummy is
generic (
some_boolean_generic : boolean := false);
port(
clk : in std_logic;
reset_n : in std_logic;
dout : out std_logic );
end dummy;

architecture dummy_arch of dummy is

begin

some_label: if some_boolean_generic = false generate
dout <= '0';
else generate
dout <= '1';
end generate some_label;

end dummy_arch;


The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty
well. It's free (as in beer) - you can get it from Altera's website.

-dan

Does VHDL-2008 need to be activated?


Not activated, but the VHDL compiler, vcom, takes a command line flag to
indicate which version of VHDL you want to apply.
e.g. vcom -93
or
vcom -2008


You can also put a default version in modelsim.ini

[vcom]
; VHDL93 variable selects language version as the default.
VHDL93 = 2008


Regards,
Allan


Guest

Wed Oct 04, 2017 1:09 pm   



Sir actually I want vhdl code of dual port ram, and I didn't gets proper way information about DPR though internet

Sir its kind request to please
Send code on this email mithleshkatre22_at_gmail.com

Charles Bailey
Guest

Fri Oct 13, 2017 7:54 pm   



On 2017-10-04 06:09, sarvesh250997_at_gmail.com wrote:
Quote:
Sir actually I want vhdl code of dual port ram, and I didn't gets proper way information about DPR though internet

Sir its kind request to please
Send code on this email mithleshkatre22_at_gmail.com

Just about any textbook or reference book on VHDL will have examples of
a one-port ram, and probably a dual port ram also.

Charles Bailey


Guest

Mon Nov 06, 2017 7:23 am   



I am unable to find the code on the given link.

Weng Tianxiang
Guest

Mon Nov 13, 2017 8:18 pm   



On Thursday, December 18, 2014 at 1:05:02 PM UTC-8, Daniel Kho wrote:
Quote:
On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote:
On 05/12/2014 12:48, Anssi Saari wrote:

Is Modelsim still not implementing VHDL 2008? I have some code with the
"new" if ... generate with else branch but Modelsim 10.1e doesn't seem
to support that. Or is it just that the Altera's Starter Edition doesn't
support that? I don't have a Modelsim PE or SE installed right now... I
tried case in generate as well but it didn't work any better.

Modelsim 10.1e was released in June of 2013. Your code compiled OK in
the latest 10.3d release.

Modelsim SE is an obsolete product and replaced by Questa core.

Regards,
Hans
www.ht-lab.com




Example code, vcom -2008 says
** Error: generate_prob.vhdl(20): near "else": syntax error
(line 20 is the else generate line.)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity dummy is
generic (
some_boolean_generic : boolean := false);
port(
clk : in std_logic;
reset_n : in std_logic;
dout : out std_logic
);
end dummy;

architecture dummy_arch of dummy is

begin

some_label: if some_boolean_generic = false generate
dout <= '0';
else generate
dout <= '1';
end generate some_label;

end dummy_arch;


The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website.

-dan


Altera final Modelsim Web edition is:
Subscription Edition Stratix (V,IV)
Arria (10,V GZ,V,II GZ,II GX)
Cyclone (V,IV E,IV GX)
MAX (10,V,II)
Web Edition Arria (II GX)
Cyclone (V,IV E,IV GX)
MAX (10,V,II)

Weng Tianxiang
Guest

Mon Nov 13, 2017 8:36 pm   



On Monday, November 13, 2017 at 10:18:21 AM UTC-8, Weng Tianxiang wrote:
Quote:
On Thursday, December 18, 2014 at 1:05:02 PM UTC-8, Daniel Kho wrote:
On Friday, 5 December 2014 22:24:15 UTC+8, HT-Lab wrote:
On 05/12/2014 12:48, Anssi Saari wrote:

Is Modelsim still not implementing VHDL 2008? I have some code with the
"new" if ... generate with else branch but Modelsim 10.1e doesn't seem
to support that. Or is it just that the Altera's Starter Edition doesn't
support that? I don't have a Modelsim PE or SE installed right now... I
tried case in generate as well but it didn't work any better.

Modelsim 10.1e was released in June of 2013. Your code compiled OK in
the latest 10.3d release.

Modelsim SE is an obsolete product and replaced by Questa core.

Regards,
Hans
www.ht-lab.com




Example code, vcom -2008 says
** Error: generate_prob.vhdl(20): near "else": syntax error
(line 20 is the else generate line.)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity dummy is
generic (
some_boolean_generic : boolean := false);
port(
clk : in std_logic;
reset_n : in std_logic;
dout : out std_logic
);
end dummy;

architecture dummy_arch of dummy is

begin

some_label: if some_boolean_generic = false generate
dout <= '0';
else generate
dout <= '1';
end generate some_label;

end dummy_arch;


The ModelSim-Altera version 10.1b (Apr 2012) supports VHDL-2008 pretty well. It's free (as in beer) - you can get it from Altera's website.

-dan

Altera final Modelsim Web edition is:
Subscription Edition Stratix (V,IV)
Arria (10,V GZ,V,II GZ,II GX)
Cyclone (V,IV E,IV GX)
MAX (10,V,II)
Web Edition Arria (II GX)
Cyclone (V,IV E,IV GX)
MAX (10,V,II)


Does it work for me if I download only the ModelSim compiler system without any device support. Because at the moment I don't have any Altera device selected and targeted, and try to determine if my design simulation works independently.


Guest

Mon Jan 22, 2018 6:52 pm   



On Tuesday, March 15, 1994 at 1:38:36 AM UTC+5:30, Habibie wrote:
Quote:
Could someone please email me a copy of the above subject? I am relatively
new to VHDL language. I would like to simulate an 8-bit shift register.

Thank you very much.
-habibie_at_srse.fiu.edu

Note: Sorry for previous wrong post.


Can someone help me to simulate n-bit shift register using for generate?

rickman
Guest

Mon Jan 22, 2018 11:47 pm   



akshalovelord_at_gmail.com wrote on 1/22/2018 11:52 AM:
Quote:
On Tuesday, March 15, 1994 at 1:38:36 AM UTC+5:30, Habibie wrote:
Could someone please email me a copy of the above subject? I am relatively
new to VHDL language. I would like to simulate an 8-bit shift register.

Thank you very much.
-habibie_at_srse.fiu.edu

Note: Sorry for previous wrong post.

Can someone help me to simulate n-bit shift register using for generate?


Have you found the it in a book? Do you understand what the book says? Do
you have questions?

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998


Guest

Fri Mar 23, 2018 2:45 pm   



On Friday, October 17, 1997 at 10:00:00 AM UTC+3, Scott L Baker wrote:
Quote:
Hi,

I'm looking for a compilable version of the PD32 processor
described in Peter Ashenden's VHDL cookbook. I have the
Word dooument which I could convert to text and extract
the VHDL, but I was hoping that the files are already available
in text format somewhere.

Any help would be greatly appreciated.

Thanks,

Scott L. Baker

Sorry, forgot to include my email address: scott_l_baker_at_ccm.jf.intel.com


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