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Thomas Stanka
Guest

Wed Oct 28, 2015 11:10 am   



Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman:
Quote:
On 10/27/2015 3:21 PM, Mark Curry wrote:
To be honest, it has been so long that I don't remember all of the
reasons.
[..]
I know there are other issues with them as well, so they are best
forgotten.


The major issue with std_logic_arith and similar (std_logic_unsigned,...) is that they are NOT standardized. They are tool dependend (original from Synopsys) and from LRM point of view illegal extensions to libray IEEE, as this library shall contain only standarized packages.
If simulation and synthesis result for these packages differ, you have nobody to complain about (beside the code autor, who dares to use non standard)..

Quote:
In addition to numeric_std, there are new packages for signed and
unsigned arithmetic on SLV, (std_logic_signed and std_logic_unsigned).
These new packages will have the same issue of not working together
since they define the same operator on the same types, but otherwise
will work ok. I just use signed and unsigned types from the std_numeric
library. Life is good.


Std_logic_unsigned and std_logic_signed are not "new packages" compared to numeric_std, they are extensions from Synopsys for the std_logic_arith and usually used in combination with arith with similar issues than arith alone.

regards,

Thomas

rickman
Guest

Thu Oct 29, 2015 7:30 am   



On 10/28/2015 5:10 AM, Thomas Stanka wrote:
Quote:
Am Dienstag, 27. Oktober 2015 22:06:23 UTC+1 schrieb rickman:
On 10/27/2015 3:21 PM, Mark Curry wrote: To be honest, it has been
so long that I don't remember all of the reasons.
[..]
I know there are other issues with them as well, so they are best
forgotten.

The major issue with std_logic_arith and similar
(std_logic_unsigned,...) is that they are NOT standardized. They are
tool dependend (original from Synopsys) and from LRM point of view
illegal extensions to libray IEEE, as this library shall contain only
standarized packages. If simulation and synthesis result for these
packages differ, you have nobody to complain about (beside the code
autor, who dares to use non standard).

In addition to numeric_std, there are new packages for signed and
unsigned arithmetic on SLV, (std_logic_signed and
std_logic_unsigned). These new packages will have the same issue of
not working together since they define the same operator on the
same types, but otherwise will work ok. I just use signed and
unsigned types from the std_numeric library. Life is good.

Std_logic_unsigned and std_logic_signed are not "new packages"
compared to numeric_std, they are extensions from Synopsys for the
std_logic_arith and usually used in combination with arith with
similar issues than arith alone.


Yes, sorry, I got my names mixed up. I meant to say
"numeric_std_unsigned and numeric_std_signed". I'm actually not sure
how widely these are supported. I only find 1600 hits on a google
search for numeric_std_unsigned and only about 100 for
numeric_std_signed. But I find them both mentioned as part of VHDL-2008
at the Doulos site, so I figure they know what they are talking about...
maybe.

--

Rick


Guest

Mon Jan 04, 2016 6:31 pm   



hi sir.....
iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+.
i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table...
is there any concept of getting 6b and 4b in encoder(rd- and rd+).

rickman
Guest

Tue Jan 05, 2016 12:41 am   



On 1/4/2016 11:31 AM, ravalitngp_at_gmail.com wrote:
Quote:
hi sir.....
iam trying to understand the lookup table for 8b/10b encoder..but its not getting to how the values are come for rd- and rd+.
i have a doubt on lookup tables on 8b/10b encoder..please give me clear explanation of 8b/10b encoder and how its come 6b and 4b in table...
is there any concept of getting 6b and 4b in encoder(rd- and rd+).


Wikipedia seems to explain this pretty well.

https://en.wikipedia.org/wiki/8b/10b_encoding#How_it_works_for_the_IBM_code

It appears that the 8b/10b code is actually done by concatenating a pair
of codes, 5b/6b and 3b/4b. Read the wiki page and come back with any
questions you have on it.

I have a question for you. Are rd+ and rd- differential signals or two
separate signals from your hardware? Do you know what the waveforms
look like on these signals?

--

Rick


Guest

Mon Jan 11, 2016 5:16 pm   



iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables..

rickman
Guest

Tue Jan 12, 2016 6:33 am   



On 1/11/2016 10:16 AM, ravalitngp_at_gmail.com wrote:
> iam doing project on 8b/10b encoder...idnt know how the lookup tables values came??please give me the explanation of the lookup tables..

You have unencoded data bits which you use as an address to fetch the
data from the encode lookup table for the encoded data. In reverse you
have encoded data which you use as an address into a decode table to
fetch the decoded data.

I'm not sure I understand your question.

--

Rick


Guest

Wed Feb 03, 2016 4:35 pm   



Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

rickman
Guest

Wed Feb 03, 2016 10:51 pm   



On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Quote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.


You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick


Guest

Thu Feb 04, 2016 12:35 am   



On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
Quote:
On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick


thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too.......

Purna

Nicolas Matringe
Guest

Thu Feb 04, 2016 6:22 am   



Le 03/02/2016 23:35, purnachandrarao.b_at_gmail.com a écrit :
Quote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting. But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......


Use a process:

monitor : process(monitored_signal)
begin
report "monitored_signal has changed" severity note;
end process monitor;

I think messages are time-stamped by he simulator. In case they're not,
adding a time stamp to the message is left as an exercise.

Nicolas

rickman
Guest

Thu Feb 04, 2016 9:07 am   



On 2/3/2016 5:35 PM, purnachandrarao.b_at_gmail.com wrote:
Quote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.


I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


> But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick


Guest

Thu Feb 04, 2016 11:49 am   



On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote:
Quote:
On 2/3/2016 5:35 PM, purnachandrarao.b_at_gmail.com wrote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick


sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response

Purna

rickman
Guest

Thu Feb 04, 2016 9:36 pm   



On 2/4/2016 4:49 AM, purnachandrarao.b_at_gmail.com wrote:
Quote:
On Thursday, 4 February 2016 03:07:27 UTC+1, rickman wrote:
On 2/3/2016 5:35 PM, purnachandrarao.b_at_gmail.com wrote:
On Wednesday, 3 February 2016 16:51:52 UTC+1, rickman wrote:
On 2/3/2016 9:35 AM, purnachandrarao.b_at_gmail.com wrote:
Hai everyone,

i am working on the FPGA and my task is to show the time-stamps whenever the signal changes as the "$monitor" verilog command shows. but i am using VHDL, please help me which command in VHDL works same as "$monitor" command.

You can try the assert command. When the assertion is not true it can
print a report that typically includes a time stamp by the simulator.
No need to actually code up the time I believe.

--

Rick

thanks for the answer but the assert will use for the result which we are not expecting.

I don't know what you mean by "the assert will use for the result which
we are not expecting". If you mean the assert statement is for errors,
that is not true. It does not care what you put in the assert statement.
You can use "assert not signal_name'event report "signal changed"
severity NOTE" to give a report each time the signal changes. "signal
changed" is anything you wish to report, but I think the time is
reported always.


But i like to print the signals with time whenever the signal changes in the given parameters. please check the $monitor verilog command for better understanding. I want the exactly the same output in VHDL too......

Rather than ask me to learn Verilog, how about you let me show you how
to use VHDL? Then you can do what you want with VHDL. Asking people to
spoon feed you is not a good way to get help.

--

Rick

sorry Rick, i don't mean that way.... i tried using the assert but i am getting the other results what i am not expecting. so i asked you in that way... i will try again, thanks for the response


Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick


Guest

Fri Feb 05, 2016 11:15 am   



Quote:
Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick


Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement.

rickman
Guest

Fri Feb 05, 2016 9:23 pm   



On 2/5/2016 4:15 AM, purnachandrarao.b_at_gmail.com wrote:
Quote:
Nicolas gives you a another answer and actually gives code. He skips
the assert part of the statement and only uses the report although it
has to be used in a process since report alone is only a sequential
statement. Assert is either sequential or concurrent so can be used in
a process or an architecture.

With the example I provided you should get a report every time the
signal changes. What are you seeing?

--

Rick

Rick, Thank you very much for the suggestions. Finally i achieved what i want to implement.


Glad it worked out.

--

Rick

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