Clock Edge notation

Serkan wrote:
 It takes two much time to simulate using that method.
 Is not there any way to do it without the testbench writing the
values?

Is your intent to test the ram design?
Finding the init data does not prove
that the ram works.

      -- Mike Treseler

Fredxx wrote:

At the same time blind reliance of simulators is just as bad.

As is blind reliance on anything.

There is the old saying garbage in = garbage out.

An rtl sim is a pretty good garbage filter.
It is only sufficient with a well-tested set of design rules.

In the past I have also come across instances where simulation has taken
so
long, and created such large files, that reality has been quicker with a
few
debugging flags in the code!

I have worked on projects where a few debugging
flags in the code would never have found
all of the logical errors.

A good testbench doesn't produce large files.

It reports pass or fail.

Hmm - perhaps you're interfacing with an external IC. Are you going to tell
me you'd blindly write a testbench without confirming that your interface in
real hardware is correctly understood?

It's clear you've never got a PCI or PCIe interface working without
resorting to the likes of chipscope, where reality doesn't even match
signals as per standards.

We purchased a PCIe core that came with a testbench.
I just worked.

Fredxx wrote:

Hmm - perhaps you're interfacing with an external IC. Are you going to
tell me you'd blindly write a testbench without confirming that your
interface in real hardware is correctly understood?

Standard interfaces are well documented.
Certainly I have to verify a few things on the bench,
but starting with a sim improves my odds.

It's clear you've never got a PCI or PCIe interface working without
resorting to the likes of chipscope, where reality doesn't even match
signals as per standards.

We purchased a PCIe core that came with a testbench.
I just worked.

"Mike Treseler" <mtrese...@gmail.com> wrote in message

news:7akg5eF1tmmprU1_at_mid.individual.net...

Fredxx wrote:

At the same time blind reliance of simulators is just as bad.

As is blind reliance on anything.

There is the old saying garbage in = garbage out.

An rtl sim is a pretty good garbage filter.
It is only sufficient with a well-tested set of design rules.

Hmm - perhaps you're interfacing with an external IC.  Are you going to tell
me you'd blindly write a testbench without confirming that your interface in
real hardware is correctly understood?

It's clear you've never got a PCI or PCIe interface working without
resorting to the likes of chipscope, where reality doesn't even match
signals as per standards.



In the past I have also come across instances where simulation has taken
so
long, and created such large files, that reality has been quicker with a
few
debugging flags in the code!

I have worked on projects where a few debugging
flags in the code would never have found
all of the logical errors.

Couldn't agree more.



A good testbench doesn't produce large files.

I was thinking of waveform files, where perhaps the simulation has to first
wade though a million states to start providing data.

It reports pass or fail.

You're just not living in the real world of FPGA design which ought to be a
mix of simulation and reality.  Anything else, and you are either assuming
your test bench doesn't have any flaws, or just fumbling in the dark.

On Jul 25, 6:11 pm, KJ <kkjenni...@sbcglobal.net> wrote:
/cut

Thank you very much for this excellent explanation !

I typically use down counters that are loaded with an initial value
and output a flag when reaching zero.  


I can't find this thread.  Anyone remember it and some keywords that
would let me find it?  There may be something wrong with Google
groups.  I search on "counter carry chain" and it finds *NO*

On Aug 14, 6:36 pm, rickman <gnu...@gmail.com> wrote:

I typically use down counters that are loaded with an initial value
and output a flag when reaching zero.

I can't find this thread. Anyone remember it and some keywords that
would let me find it? There may be something wrong with Google
groups. I search on "counter carry chain" and it finds *NO*

I think this is the link you're looking for. Andy's post from June 19
is the 8th one in the thread.

http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/36d78...

Kevin Jennings

I seem to recall making this work by adding an extra bit to the input
value and separating the msb of the output as the carry. I'll give
that a try.

Not specific to your down counter problem, but I posted a

On Aug 14, 6:36 pm, rickman <gnu...@gmail.com> wrote:

I typically use down counters that are loaded with an initial value
and output a flag when reaching zero.  

I can't find this thread.  Anyone remember it and some keywords that
would let me find it?  There may be something wrong with Google
groups.  I search on "counter carry chain" and it finds *NO*

I think this is the link you're looking for.  Andy's post from June 19
is the 8th one in the thread.

http://groups.google.com/group/comp.lang.vhdl/browse_frm/thread/36d78...

Kevin Jennings

Hi Rick,
Integers and such are great for sim run time, however, if you are not
getting the hardware you want, here is an array based algorithm that
only uses one carry cell to implement the zero detect. It has a few
extras that you may want to remove. BaseReg is the loadable base
register. CntReg keeps the current count value. IntReg is a
registered version of the zero detect.

Best,
Jim
SynthWorks VHDL training

TimerProc : process (Clk, nReset)
variable Dec : unsigned(CntReg'Length downto 0) ;
begin
if (nReset = '0') then
BaseReg <= (others => '0') ;
CntReg <= (others => '0') ;
IntReg <= '0' ;
elsif rising_edge(Clk) then
if (TimerSel = '1' and Read = '0') then
BaseReg <= unsigned(DataIn) ;
end if ;
Dec := ('0' & CntReg) - 1 ;
if (Dec(Dec'Left) = '1') then
CntReg <= BaseReg ;
else
CntReg <= Dec(CntReg'Range);
end if ;
IntReg <= Dec(Dec'Left) ;
end if ;
end process ;