Clock Edge notation

Wed Jun 24, 2009 7:43 pm   

"Muzaffer Kal" <kal_at_dspia.com> wrote in message
news:4ul445tbv9klgrceumj15dd2jfcpjp4raq_at_4ax.com...

Different types of flip flops can be inferred by VHDL. Not all have to use
the global clock, or even a clock as such.

True - if it was my problem, I would look at the logic it creates, but at
the moment I don't have time.

Wed Jun 24, 2009 7:53 pm   

On Jun 24, 6:15 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

Current synthesis tools would probably have an issue with this, but
there's no good reason for it. DDR synthesis (though not the same as
independent clock, dual port memories) needs it anyway. Some synthesis
tools support dual clock processes, just not writes to the same var/
sig on both clocks. The only time this example does not behave like a
true dual clock/port ram is when two writes are attempted to the same
address at exactly the same time, which is not even defined for the
real HW. Good system design makes that case meaningless anyway.

Andy

Wed Jun 24, 2009 10:02 pm   

On Jun 24, 10:57 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

The vendors say, "Instantiate the component from the library," which
neatly sidesteps the difficult work of actually enabling such
inference.

-a

Thu Jun 25, 2009 3:43 am   

On Jun 24, 10:57 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:


The truth is that current FPGA Synthesis tools quite often do a poor
job (not counting trivial cases here) in inference of FPGA vendors'
macros. From the other hand FPGA vendors want users to instantiate
their macros (and so to be locked into their devices) and make it very
easy to configure and generate the code for instantiation using
proprietary vendor tools.
So majority of users prefers to instantiate the macros as a better
alternative to make the Synthesis tools infer the necessary structure
(and lose sometimes days on debugging different synthesis attributes,
directives etc...)
Just wanted to offer a possible explanation in answer to your
question, Jonathan :^)

Theoretically, independent FPGA synthesis tools vendors (Mentor,
Synopsys) should be interested for users to create a vendor
independent code. This way they'll have a much stronger case for multi-
vendor tools...

Alex Yourovski

Thu Jun 25, 2009 10:03 am   

Jonathan Bromley <jonathan.bromley_at_MYCOMPANY.com> writes:


You have mine!

And thanks for sharing the results of your investigations with us all!

Cheers,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Thu Jun 25, 2009 10:55 am   

Do you mean don't simulate the P&R'd design, or not at all?



Nial.

Thu Jun 25, 2009 2:09 pm   

On Jun 25, 6:55 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:

This thread has brought up several very interesting themes. I'd like
to add my two cents to each.

1) Synthesis templates for RAMS. I think what Jonathan is doing is a
great idea. I'd love to see a better definition of what cross-device
code patterns are safe to use and supported by which tools. From
experience, I can say that I've done it right for a few key designs,
and managed to leverage off of that by wrapping this inference in an
entity, giving me a device-independent (more-or-less) codebase but
still requiring structural coding around the RAM. It's not ideal by a
long shot. But by enforcing good version control discipline through
the organization and introducing a mindset that says "don't fiddle
around with a perfectly good library module, use it as-is or not at
all", we have managed to reduce the number of times designers sit
there, asking the same questions: "I only changed one line of code;
why did it start making distributed RAM? What were those attributes
again? When I don't use the read port how do I stop the synthesizer
from complaining?" and so on and so on.

2) Clocks versus asynchronous logic. My view of this is that clocks
are both an obvious physical thing (as anyone who flies a scope for
living well knows) as well as an abstraction. This abstraction is
what constitutes the "contract", or point of demarcation between high-
level circuit digital designer, and the guy who actually codes the
gate-level RAM and control logic. The job of the low-level transistor
guy is to provide a circuit that acts as if the clock abstraction is a
true representation of what actually happens inside. He may use flops,
latches, vernier timing thingies, or whatever the heck he needs. But
he *must* obey the clock-concept contract. The job of the high-level
(FPGA application developer) is to make use of the clock concept
abstraction in order to make his design synchronous, which implies
robustness, maintainability, and all the other virtues that regular
posters here know so well.

3) People who don't do simulation? Definitely. I've help manage the
change in an organization growing from a couple of FPGA guys to a
fairly well-oiled FPGA talent pool with established version control,
substantial as-is module re-use, and an ingrained mindset that a
modules doesn't get released without a scripted, regressionable
testbench. They're two points at opposite ends of a continuum of
process, but I see a lot of real work in industry done at both ends.

The "garage shop" FPGA approach typically has some guys who learned
VHDL in school, then got thrown into the deep end alone, or who "came
up through the ranks" from CPLDs and board design. No VC, no software
techniques, no libraries, packages, functions or elegant code in the
source. Hack job, in short. Two of these guys working on the same
project may often be running different tool versions, and not even be
able to load the design as-is from the other guy's sources, without a
lot of manual GUI fiddling to reset paths, manually link in the right
libraries, and so on. There's little chance of even building the same
design twice in a row. These are the guys who throw their bitfile onto
the board, and if it doesn't work, start writing some testbenches
(aww, do I *have* to do that... what a pain). They don't want to
simulate because its too hard/too long to sim the whole chip, and
because there's poor structure and/or modularity in their own code to
begin with, so it's also too hard to isolate a portion and make a
simple test for it, too.

The "pro" is at the other end of the continuum. Most of the regular
posters here try to answer the "garage guys" with answers that will
point them in the direction of becoming a "pro". It's a lot more
work, but there's a lot of benefit to being able to release a chip
that you know that anyone on your team can build again, bit/UCF/source-
accurately, when you're on vacation.

Of course, some "pros" work in garage shops. But the Big Tool (Big
Two?) vendors tend to cater most of their tools to the garage shop
guys. Everything can be set by clicking on a GUI button. Everything
about a project is stored in unreadable binary files. They try to
force you into their half-assed version control scheme, if they offer
one at all. How are you ever going to share designs or document them
for the future that way? And all of the "sex appeal" about the new
devices is put into the GUI, the new buttons that you can click on,
and the new auto-wizards (that don't usually have a mode to generate
output from anything other than unreliable, unrepeatable user mouse
clicks). ( I tend to think of this emphasis on sexy GUI tools leading
then to bad project practices as being akin to drug dealers pushing
crack in the schoolyards, but that would get me in trouble with my
local FAEs so I'll refrain :-)

Don't get me wrong... I had a lot of fun as a garage guy myself. I
built some pretty damn fine hardware "back in the day" before I even
had the option of simulating my code. But I agree, there are still a
lot of guys who view testbenches and simulation as something painful
and only to be done if really necessary. In truth, it's like pretty
much everything else in life: you get out more when you put in more
work.

OK, I'm done ranting now :-)

- Kenn

Thu Jun 25, 2009 3:44 pm   

On Thu, 25 Jun 2009 07:33:06 -0700 (PDT), rickman <gnuarm_at_gmail.com>
wrote:


Whether they simulate their designs, (before downloading & testing on
the board).
-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Thu Jun 25, 2009 4:33 pm   

On Jun 24, 2:11 pm, Muzaffer Kal <k...@dspia.com> wrote:

I missed something. What question exactly?

Rick

Thu Jun 25, 2009 6:53 pm   

On Thu, 25 Jun 2009 11:11:59 -0700 (PDT), rickman wrote:


No, I don't think so. I meet loads of engineers in
my training work, and it is rare indeed to find a
stupid one. Some are quite extraordinarily smart.

However, engineers do very complicated, occasionally
very difficult, and certainly very arcane things.
I reckon they get used to the idea that no-one they
meet is likely to be able to help them much. So
they get very narrowly focused on the (perceived)
task at hand, and lose the ability to look outside
their narrow concerns. (I'm sure I fall into that
trap frequently myself.) That narrowness can
easily come across as arrogance and/or reluctance
to accept advice.

Getting software folk and digital designers
talking to each other would be a big step in
the right direction. Sometimes that works well,
but certain project management styles (as in Rick's
story) go a long way towards preventing it.

Re-skilling, as often as you get the chance, is
a pretty good antidote to belief that you know
it all. Career circumstances don't usually make
that easy to do, sadly.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley_at_MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thu Jun 25, 2009 8:11 pm   

On Jun 25, 11:44 am, Muzaffer Kal <k...@dspia.com> wrote:

Oh, I see. The last place I worked was a pretty good sized defense
contractor making push to talk radios. They actually had the FPGA
group under the software department because they felt it has more in
common (such as using version control on the source files). I was in
the hardware group and so not allowed to work on anything in the FPGA,
including code to test my hardware. One of the other "hardware"
engineers gave a "training" lecture to the entire hardware department
(most of who were RF designers) about FPGA design. His method of
doing timing analysis was to run a simulation!!! I had to stop him
right there are point out that was what static timing analysis was
for. He said that was not needed, since he could do a post route
simulation. How insane is that!!!!!????

The other side of the coin was that they had a newbie working the FPGA
code which was a collection of a couple of UARTs, I2C and a custom
serial interface. Instead of simulating (or maybe just not a very good
simulation) they were relying on the Xilinx logic analyzer tool. I
can't think of a more painful way of doing the initial debug. I was
asked to help them get the FPGA to load a bit file the first time and
they didn't want to listen much to me. They had five (yes FIVE!!!)
engineers working on it including a very senior engineer and a first
level manager. No one could seem to figure out what was wrong. I had
to wedge my way into the fray and started showing them the few simple
steps you have to take to get it going. I kept pointing out that you
need to give a few extra clocks at the end of downloading the file to
get the part out of configuration mode and they kept telling me that
was already tried. But the symptoms all pointed to this as the
problem. So I had to beat on it over and over again until finally
someone realized that they had tried adding strobes up to 64k as a
magic bullet and when that didn't make it work (they had more than one
problem) it was removed entirely! So they finally listened to me for
a moment and the devices loaded... FIVE engineers couldn't figure
that out!!!

So we have engineers who don't believe it is productive to run
simulation, engineers who believe they don't need to use static timing
analysis and engineers who can't debug their way out of a paper bag!!!

Are engineers the stupidest people in the world or is it just defense
contractors?

Rick

Fri Jun 26, 2009 1:05 pm   

"Muzaffer Kal" <kal_at_dspia.com> wrote in message
news:csq445t6012cnufggai343t9jqptbe2pnd_at_4ax.com...

At the same time blind reliance of simulators is just as bad. There is the
old saying garbage in = garbage out. Personally I choose a mix as an early
misunderstanding can otherwise waste an inordinate amount of time.

In the past I have also come across instances where simulation has taken so
long, and created such large files, that reality has been quicker with a few
debugging flags in the code!

Each to their own.

Fri Jun 26, 2009 3:35 pm   

On Jun 25, 1:53 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

Most of the time when I mention that FPGA/ASIC engineers could learn a
trick or three from their SW brethren, I get bombarded with "FPGA/ASIC
design is not SW!" True enough, but the discipline of code design, and
to a lesser extent testing, is very much the same between the two. The
requirements for the code are much different (usually), but the method
in which complex requirements must be analyzed, broken down, designed
into code and verified are incredibly similar. SW has developed over
the years many techniques for dealing with the complexity of all
things coded, and we HW engineers can learn an awful lot from them
about at least that.

I have worked with some SW engineers that fairly quickly grasped the
HW nature of HDL code, and some that didn't ever get it. I have also
worked with some HW engineers that grasped the SW nature of their
design, and some that didn't. Those that do understand the
similarities and the differences between the two, and exploit the
similarities while observing the limitations of the differences, are
the ones I want on my team.

There are often organizational turf battles that get in the way of
honest exchange of ideas and solutions between SW and HW. It seems to
be the mavericks from both camps that tend to understand the common
ground and then exploit it, to the benefit of both.

Andy

Fri Jun 26, 2009 5:37 pm   

Andy wrote:


I agree. Thanks for the posting.

I would only add that it is curious that the same
software engineers that insist on careful version
control and unit testing for their own code,
are often content to accept a binary fpga image file
directly into their firmware without insisting
on having any of the supporting sources or build processes.

-- Mike Treseler

Fri Jun 26, 2009 5:51 pm   

Fredxx wrote:


As is blind reliance on anything.


An rtl sim is a pretty good garbage filter.
It is only sufficient with a well-tested set of design rules.


I have worked on projects where a few debugging
flags in the code would never have found
all of the logical errors.

A good testbench doesn't produce large files.
It reports pass or fail.

-- Mike Treseler