Clarification required to do my Project

Thu Feb 24, 2011 1:10 pm   

Hi everyone,
I am trying to implement a pattern matching algorithm for
Intrusion Detection system in FPGA's .The algorithm i ve developed has
lesser number of iterations compared to the existing algorithms. I ve
developed and tested it using "C"...But i get lot of errors while
compiling it in verilog.I ve listed down the problems im facing now.If
anyone knows the solution please reply asap.

-->How can i declare a string in verilog??
-->when i synthesize the verilog code in Xilinx i get a
error XST-1312 "Loop has iterated 64 times"...How can i correct the
error??
-->How can i view the timing report before and after
implementing in FPGA??
-->how to define a multi dimensional array??
-->how to reduce area and cost of FPGA by verilog
code??
-->what parameters can i show the simulated output??

with regards
AP

Thu Feb 24, 2011 4:14 pm   

Pandiarajan <pandiarajan01_at_gmail.com> wrote:


Without knowing which algorithm you are using, I always
recommend the systolic array architecture for pattern matching.

You might look into it, anyway.

Otherwise, C doesn't translate to verilog so well.

-- glen

Mon Feb 28, 2011 12:29 pm   

On Feb 24, 7:14 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

Thank yo Glen.i will go through it.
can yo explain how can i view the timing report before and after
implementing in FPGA ??

Tue Mar 01, 2011 9:32 pm   

I find that a standard editor works just dandy in opening the file.
Often is also d
isplayed with the tool that you are using to generate
it if you are using a GUI.

Viewing the report before its created is very difficult and I haven't
figured out how to do that.

Mike