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Guest

Mon Oct 04, 2004 11:49 am   



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Torgny Johansson
Guest

Mon Oct 04, 2004 11:49 am   



Hi again!

As I said before we're trying to create a cell library that will work with
place and route tools. We seriously need to minimize the time used so I
wonder which files are absolutely necessary for this?

What we've figured out so far is that we need the layout for the cells, a
lef file describing the technology and the cells and possibly an abstract
view of the cell?

What else is needed? We don't need a TLF unless we wan't time driven
placing right? Is the abstract needed? Do we need any kind of timing files
for basic place and route?

Thanks!

Regards Torgny

--
Using Opera's revolutionary e-mail client: http://www.opera.com/m2/

Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   





Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   





Erik Wanta
Guest

Mon Oct 04, 2004 11:49 am   





Rob W
Guest

Mon Oct 04, 2004 11:49 am   





Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   



Good man! Glad to see someone else who sees the problems from
the dreaded callbacks!

I've made some comments on this in the past:

http://groups.google.com/groups?q=callback+andrewb+group:comp.cad.cadence&hl=en&lr=&ie=UTF-8&group=comp.cad.cadence&selm=3ccf6f99.514509%40news.cadence.com&rnum=3

http://groups.google.com/groups?q=callback+andrewb+group:comp.cad.cadence&hl=en&lr=&ie=UTF-8&group=comp.cad.cadence&selm=vcmhru88q9kbp2bqgif1djkn81q5djfjje%404ax.com&rnum=4

Unfortunately (as I've pointed out before), they appear attractive
for kit developers, but often they're not the ones using the tools...

Andrew

On Wed, 09 Jul 2003 14:36:12 +0200, Andreas Dreyfert
<andreas_deryfert_at_hotmail.com> wrote:

Quote:
Hi,All

I have a problem that has bothered me for a while that is caused by the
design kit for icfb.

Why do many design kits use callbacks in the CDF to calculate parameters
such as source/drain area of transistor?
When things are implemented this way you can not use some functions in
the simulator. For example you can not sweep the width of a transistor
and get correct results because the parasitics were calculated for the
initial width in the schematics

Would it not be better to implement such function in the models? So that
functions such as sweep can be used.

This is no big problem but it makes the tool more difficult to use.

Regards,
Andreas

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

Saqib Q Malik
Guest

Mon Oct 04, 2004 11:49 am   



Jay,
My observation has been that any change in the schematic window (and do
a check-n-save) gets the attention of the GUI resulting in a new netlist.
The telltale sign is that the log window that comes to the top is reset and
simulator output from only that run is shown. The problem shows up
especially after making changes to the analysis setup in the ADE GUI. After
such a change I could tell my changes are not getting propagated and
simulated when I noticed the log window kept appending more simulator output
in the same window. For example, if I changed my DC analysis stop point to
3V from 2V, the output log kept showing that the simulation is running to
2V.

I tried to use the Simulation->Stop approach you mentioned, but for me that
option is grayed out once the simulation completes and after the problem I
reported occurs. I doubt this is a feature since I never saw this behavior
in 4.4.6.

I will post any response/solution from Cadence support on the subject when
it becomes available.

Thanks.
Saqib Malik
e-mail: saqib at iastate dot edu

"Jay Lessert" <jayl-news_at_accelerant.net> wrote in message
news:7109f92b.0307081131.58f6b1af_at_posting.google.com...
Quote:
"Saqib Q Malik" <sqmalik_at_DeleteThisIastate.edu> wrote in message
news:<be89mg$5bj$1_at_news.iastate.edu>...
Hello all. I have run into a problem with Spectre. After a few
simulations,
spectre does not use the new netlist and wants to keep on simulating the
same old netlist.

The behavior I'm used to seeing is that a running Spectre sim (in the
"Analog Design Environment" GUI) will decline to notice changes in the
netlist unless you explicitly:

Simulation->Stop

I always assumed this was a "feature". Are you seeing behavior
different from this?

-Jay-


Pete nospam Zakel
Guest

Mon Oct 04, 2004 11:49 am   



In article <5fb00e69.0307090121.6bbb3ada_at_posting.google.com> svenn.are_at_bjerkem.de writes:

Quote:
I use a pc with linux and xfree86 and a standard graphics card as a
front-end to solaris and ic50. With standard setup I have the flashing
color problem that many describe in this newsgroup. So far I have got
the impression that theonly way to solve this problem is to buy a
Matrox card and Accelerated X.

Actually, with IC5.0 all you need to do is change your root visual to
24-plane TrueColor.

The Matrox card and Accelerated-X is only necessary if you want to avoid
color flashing with IC4.4.6 or previous. If you set your root visual to
24-plane TrueColor, with XFree86 you won't be able to run IC4.4.6, but
IC5.0 will run.

-Pete Zakel
(phz_at_seeheader.nospam)

"Religion isn't knowing the answers; it's knowing there are answers."

Rob W
Guest

Mon Oct 04, 2004 11:49 am   



I appreciate your help, Andrew.

I was doing a couple of things wrong; I wasn't including the forward
slash at the beginning of the instance name, and I was specifying
hierarchy as a list of instance names from the top level, i.e.
list("I1" "I2" "M3") as in your example. The list argument threw me
off a bit. I wonder why the argument is a list instead of just a
string?

Best regards,

Robert




Andrew Beckett <andrewb_at_DELETETHISBITcadence.com> wrote in message news:<on0ogv8dpehs6h9m0ucrhe1kq8k7ov14kg_at_4ax.com>...
Quote:
Rob,

You shouldn't read from the map directory itself (or the amap) because the
format is private and liable to change (I wasn't sure from what you said
whether you were doing that or not).

However, asiMapInstanceName should work. I just checked. I had
an instance name and a net name both called "R2" at the top level
of my design:

l=list("/R2")
asiMapInstanceName("~/simulation/rcac/spectre/schematic" l) => "_inst0"

I'd run a simulation - it may not work before a simulation.
Also, you _must_ include the / at the beginning - using the leading
slash, and then slashes to delimit hierarchy (e.g. /I1/I2/M3 ) is how
it knows that you're asking for a schematic name rather than a netlist name.

Note, the function destructively modifies the list - so l afterwards
contains ("_inst0")

Regards,

Andrew.



Andreas Dreyfert
Guest

Mon Oct 04, 2004 11:49 am   



I colud not agree more with you!

But why do certain kit developers who know better still use them?
As you stated in your earlier comments they appear very attractive. But
if they limit the possible usage of your other products. One would think
that one would try to use other ways of implementing such functions then
it is possible.

I have used your skill code example from your earlier comments to get
around the problem. But if I run lots of short simulations and change
the schematic in database between every run the time consumed by
changing the database,netlisting and other stuff will be significant. If
one instead could use the alter (or other) function in spectre you would
not need to change the database or renetlist at all!

Andreas


Andrew Beckett wrote:
Quote:
Good man! Glad to see someone else who sees the problems from
the dreaded callbacks!

I've made some comments on this in the past:

http://groups.google.com/groups?q=callback+andrewb+group:comp.cad.cadence&hl=en&lr=&ie=UTF-8&group=comp.cad.cadence&selm=3ccf6f99.514509%40news.cadence.com&rnum=3

http://groups.google.com/groups?q=callback+andrewb+group:comp.cad.cadence&hl=en&lr=&ie=UTF-8&group=comp.cad.cadence&selm=vcmhru88q9kbp2bqgif1djkn81q5djfjje%404ax.com&rnum=4

Unfortunately (as I've pointed out before), they appear attractive
for kit developers, but often they're not the ones using the tools...

Andrew

On Wed, 09 Jul 2003 14:36:12 +0200, Andreas Dreyfert
andreas_deryfert_at_hotmail.com> wrote:


Hi,All

I have a problem that has bothered me for a while that is caused by the
design kit for icfb.

Why do many design kits use callbacks in the CDF to calculate parameters
such as source/drain area of transistor?
When things are implemented this way you can not use some functions in
the simulator. For example you can not sweep the width of a transistor
and get correct results because the parasitics were calculated for the
initial width in the schematics

Would it not be better to implement such function in the models? So that
functions such as sweep can be used.

This is no big problem but it makes the tool more difficult to use.

Regards,
Andreas


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd


Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   



Sorry, but this is not true. Pete knows best because he implemented it!

Only IC50 and above support 24 plane visuals directly (even if there is no
8 plane pseudocolor visual). IC442->IC446 support 24 plane root windows provided
that the X server supports an 8 plane pseudocolor visual.
xfree86 doesn't (at least this used to be true, I'm assuming it still is)
provide 8 plane psuedocolor visuals when in 24 plane root window mode, so
if you're using IC446 with it, you need to switch to 8 plane root window - and
that's when you end up with the color flashing.

Regards,

Andrew.

On Wed, 9 Jul 2003 15:57:20 -0400, "tritue" <tritue_at_comport-data.com> wrote:

Quote:
In fact IC4.46 support 24 bit color as well. The flashing color problem is
only with
IC4.45 and previous in pseudo color mode.

"Pete nospam Zakel" <pxhxz_at_cadence.com> wrote in message
news:3f0c625c$1_at_news.cadence.com...
In article <5fb00e69.0307090121.6bbb3ada_at_posting.google.com
svenn.are_at_bjerkem.de writes:

I use a pc with linux and xfree86 and a standard graphics card as a
front-end to solaris and ic50. With standard setup I have the flashing
color problem that many describe in this newsgroup. So far I have got
the impression that theonly way to solve this problem is to buy a
Matrox card and Accelerated X.

Actually, with IC5.0 all you need to do is change your root visual to
24-plane TrueColor.

The Matrox card and Accelerated-X is only necessary if you want to avoid
color flashing with IC4.4.6 or previous. If you set your root visual to
24-plane TrueColor, with XFree86 you won't be able to run IC4.4.6, but
IC5.0 will run.

-Pete Zakel
(phz_at_seeheader.nospam)

"Religion isn't knowing the answers; it's knowing there are answers."


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   



Hi Rob,

I'm not sure why it's a list - it only ever uses the first entry in the list (I
checked the code yesterday). Similarly the destructive modification of
the list contents is a concious decision - I suspect it was done when the
underlying private function was implemented to fit in nicely with the code
that used it... perhaps?

Andrew.

On 9 Jul 2003 14:26:47 -0700, malleablecandy_at_yahoo.com (Rob W) wrote:

Quote:
I appreciate your help, Andrew.

I was doing a couple of things wrong; I wasn't including the forward
slash at the beginning of the instance name, and I was specifying
hierarchy as a list of instance names from the top level, i.e.
list("I1" "I2" "M3") as in your example. The list argument threw me
off a bit. I wonder why the argument is a list instead of just a
string?

Best regards,

Robert




Andrew Beckett <andrewb_at_DELETETHISBITcadence.com> wrote in message news:<on0ogv8dpehs6h9m0ucrhe1kq8k7ov14kg_at_4ax.com>...
Rob,

You shouldn't read from the map directory itself (or the amap) because the
format is private and liable to change (I wasn't sure from what you said
whether you were doing that or not).

However, asiMapInstanceName should work. I just checked. I had
an instance name and a net name both called "R2" at the top level
of my design:

l=list("/R2")
asiMapInstanceName("~/simulation/rcac/spectre/schematic" l) => "_inst0"

I'd run a simulation - it may not work before a simulation.
Also, you _must_ include the / at the beginning - using the leading
slash, and then slashes to delimit hierarchy (e.g. /I1/I2/M3 ) is how
it knows that you're asking for a schematic name rather than a netlist name.

Note, the function destructively modifies the list - so l afterwards
contains ("_inst0")

Regards,

Andrew.



--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

Andrew Beckett
Guest

Mon Oct 04, 2004 11:49 am   



Saqib,

When you just change analysis settings and parameter settings, it does not
necessarily need to restart the simulation, but tells the simulator directly.
You would expect to see a single output log with the original simulation
followed by the new simulation in this case. However, it should reflect any
changes that have been made; if not, then that definitely needs to
be reported (I've not seen this kind of problem recently, and to be honest,
the problems in the past that I saw were really more related to schematic
changes not being renetlisted - but that was ages ago).

Regards,

Andrew.

On Wed, 9 Jul 2003 12:09:54 -0500, "Saqib Q Malik"
<sqmalik_at_DeleteThisIastate.edu> wrote:

Quote:
Jay,
My observation has been that any change in the schematic window (and do
a check-n-save) gets the attention of the GUI resulting in a new netlist.
The telltale sign is that the log window that comes to the top is reset and
simulator output from only that run is shown. The problem shows up
especially after making changes to the analysis setup in the ADE GUI. After
such a change I could tell my changes are not getting propagated and
simulated when I noticed the log window kept appending more simulator output
in the same window. For example, if I changed my DC analysis stop point to
3V from 2V, the output log kept showing that the simulation is running to
2V.

I tried to use the Simulation->Stop approach you mentioned, but for me that
option is grayed out once the simulation completes and after the problem I
reported occurs. I doubt this is a feature since I never saw this behavior
in 4.4.6.

I will post any response/solution from Cadence support on the subject when
it becomes available.

Thanks.
Saqib Malik
e-mail: saqib at iastate dot edu

"Jay Lessert" <jayl-news_at_accelerant.net> wrote in message
news:7109f92b.0307081131.58f6b1af_at_posting.google.com...
"Saqib Q Malik" <sqmalik_at_DeleteThisIastate.edu> wrote in message
news:<be89mg$5bj$1_at_news.iastate.edu>...
Hello all. I have run into a problem with Spectre. After a few
simulations,
spectre does not use the new netlist and wants to keep on simulating the
same old netlist.

The behavior I'm used to seeing is that a running Spectre sim (in the
"Analog Design Environment" GUI) will decline to notice changes in the
netlist unless you explicitly:

Simulation->Stop

I always assumed this was a "feature". Are you seeing behavior
different from this?

-Jay-


--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

Svenn Are Bjerkem
Guest

Mon Oct 04, 2004 11:49 am   



Pete nospam Zakel wrote:

Quote:
Actually, with IC5.0 all you need to do is change your root visual to
24-plane TrueColor.


Without access to the actual linux box I have to ask if the "TrueColor"
mentioned above is the key to the problem. I have xfree86 4.2 that comes
with apt-get dist-upgrade in debian unstable/testing /and/ I had to change
the settings to 24 bit in order to get IC to run at all ( I had 16-bit to
save memory, but then IC50 doesn't start.)

For the record, on http://www.xfree86.org/4.2.1/XF86Config.5.html in the
section on Visual, TrueColor is listed as one of the alternatives. I know
that I don't have that option set on the linux workstation, yet ...

--
Svenn Bjerkem

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