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Cascading binary counter ICs

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Peter
Guest

Wed Nov 29, 2017 2:21 pm   



Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?

I realize this approach is about forty years out of date and it could
probably be done far more elegantly with a single suitably programmed
PIC or similar processor. But I know exactly nothing about PIC
programming and I do have plenty of ripple counters in the parts box.
Peter.

Ian Field
Guest

Wed Nov 29, 2017 9:50 pm   



"Peter" <noemail_at_pigpond.com> wrote in message
news:ovm8ob$3od$2_at_dont-email.me...
Quote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours and
then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with a
CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I feed
that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output finally
goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?

I realize this approach is about forty years out of date and it could
probably be done far more elegantly with a single suitably programmed PIC
or similar processor. But I know exactly nothing about PIC programming and
I do have plenty of ripple counters in the parts box.
Peter.


AFAICR: you can pre load a 7490 to divide by 3, which is basic to the
chronology.

There is now a dual BCD counter, something like 74290 - which should be
available as HC or HCT.

Not too sure if you still get all the pre load pins, but you can gate for
premature reset anyway.

The underlying logic is what it is - you can construct it with a couple of
dividers and some glue logic.

Computer Nerd Kev
Guest

Wed Nov 29, 2017 11:47 pm   



Peter <noemail_at_pigpond.com> wrote:
Quote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?


No problem with the ripple counters themselves. Though depending on your
application a problem may be faced with the propogation delays of the
many stages causing glitches to appear at the decoded output.

The delay between gates changing state after the clock pulse means
that there will be periods (of a length in the order of microseconds)
where the outputs match the required count in error, because each one
changes before the next.

If the output is to an LED or similar, this won't matter, but if it
is to another logic input, it may be advisable to use an RC filter
on the output of the AND gate decoding the counter state, along
with a schmitt buffer on the filter output.

If you wanted to count to around 9hrs and 27hrs, you could use
a single 4521 on the 8Hz output of the first 4020 to output
9hrs on its Q18 output, and 27hrs with both Q18 and Q19 HIGH.
It might be possible to do 8 and 24hrs with an input clock
higher than 8Hz. 64Hz might work, AND Q18, Q19 and Q20 for
8hrs... Q18, Q20 and Q22 for 24hrs? You'd better check for
yourself.

--
__ __
#_ < |\| |< _#

Peter
Guest

Thu Nov 30, 2017 4:19 am   



On 30/11/2017 7:47 AM, Computer Nerd Kev wrote:
Quote:
Peter <noemail_at_pigpond.com> wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?

No problem with the ripple counters themselves. Though depending on your
application a problem may be faced with the propogation delays of the
many stages causing glitches to appear at the decoded output.

The delay between gates changing state after the clock pulse means
that there will be periods (of a length in the order of microseconds)
where the outputs match the required count in error, because each one
changes before the next.

If the output is to an LED or similar, this won't matter, but if it
is to another logic input, it may be advisable to use an RC filter
on the output of the AND gate decoding the counter state, along
with a schmitt buffer on the filter output.

If you wanted to count to around 9hrs and 27hrs, you could use
a single 4521 on the 8Hz output of the first 4020 to output
9hrs on its Q18 output, and 27hrs with both Q18 and Q19 HIGH.
It might be possible to do 8 and 24hrs with an input clock
higher than 8Hz. 64Hz might work, AND Q18, Q19 and Q20 for
8hrs... Q18, Q20 and Q22 for 24hrs? You'd better check for
yourself.


Very helpful, CN Kev. No CD4521 in stock but I've ordered a few for
future exploration. You gave me one good tip which was taking 8Hz from
the first CD4020 to clock a CD4521. I suddenly realized that I could
pick a higher frequency off the first CD4020 to clock a second CD4020 so
its outputs Q1 to Q14 have periods that can be decoded to give me 8rs
and 24 hrs.Some quick scratching with pencil and paper suggests that it
can be done. That will reduce my CD4020's to two. I need to have a 1Hz
clock tick too but that can be achieved by dividing the 2Hz at Q14 of
the first CD4020 with half of a dual flipflop. That increases the
chip-count by one again but I'm not constrained much by PCB space or
power budget.
I note your cautions about glitches caused by the propagation delay.
Maybe I'll be able to see any glitches with my Rigol DSO and if there
are any I can follow your suggestion of RC filter and Schmitt buffer. My
"design", if you can call it that, features a hex inverter chip that
will use one gate to take the low at the 24 hour mark and apply a high
to all the reset pins of the counters. I guess I can select a Schmitt
type hex inverter. I could use two of the five spare inverter gates to
make non inverting Schmitt buffers if required.
Much thanks.
Peter

Jasen Betts
Guest

Thu Nov 30, 2017 7:51 am   



On 2017-11-29, Peter <noemail_at_pigpond.com> wrote:
Quote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.


I'd have suggested a CD4060 for the first counter, ans they can
connect directly to the crystal.

Quote:
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?

I realize this approach is about forty years out of date and it could
probably be done far more elegantly with a single suitably programmed
PIC or similar processor. But I know exactly nothing about PIC
programming and I do have plenty of ripple counters in the parts box.
Peter.


all the from-scratch CMOS clock designs I've encountered used divide by
five and divide by three stages in addition to the divide by two stages.
(some used divide by 6 and divide by 10 stages)

to gwt an 8-hour periodic signal from 2hZ you need to count to 57600

which is 256 * 225

225 is 128 + 64 + 32 + 1

So, and output 9 snd 14 of the second 4020 with outputs 1 and 2 of
the third and feed that back to the reset pins of those two counters.

output 2 of the third of will have a high to low transition after 8
hours from reset (it spends most of its time low)

invert that* and use it to clock a divide by 3 counter to get the 24 hour count.

(*) or use a counter with falling edge triggering

--
This email has not been checked by half-arsed antivirus software

Jasen Betts
Guest

Thu Nov 30, 2017 8:05 am   



On 2017-11-29, Computer Nerd Kev <not_at_telling.you.invalid> wrote:
Quote:
Peter <noemail_at_pigpond.com> wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?

No problem with the ripple counters themselves. Though depending on your
application a problem may be faced with the propogation delays of the
many stages causing glitches to appear at the decoded output.

The delay between gates changing state after the clock pulse means
that there will be periods (of a length in the order of microseconds)
where the outputs match the required count in error, because each one
changes before the next.


No, because they are ripple copunters and only count upwards, and
changes (carries) propogate leftwards (by place value) they never will:
all the glitch states are lower than the correct count. ie "missing ones"
and so will never trigger AND logic early

synchronous counters on the other hand can lead to glitches depending
on which wire has the most capacitance etc...

say you're looking for the 225 (11100001 binary) you only need to look
for the ones, the zeros can be don't care because the first match for
that pattern (111xxxx1) comes at count 225

--
This email has not been checked by half-arsed antivirus software

~misfit~
Guest

Thu Nov 30, 2017 9:51 am   



Once upon a time on usenet Peter wrote:
Quote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down
with a CD4020 14 stage ripple counter to give 2Hz at the 14th stage,
then I feed that to the clock pin of a second CD4020. A 1Hz or 1
second clock "tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter
outputs with simple hardwired diode gates to pick off the exact
elapsed times I want. The only question is whether there could be any
problems with cascading three CD4020's?

I realize this approach is about forty years out of date and it could
probably be done far more elegantly with a single suitably programmed
PIC or similar processor. But I know exactly nothing about PIC
programming and I do have plenty of ripple counters in the parts box.
Peter.


I don't suppose that this helps:
https://youtu.be/bn3uYJrXhhw

(Bigclive talking logic and timers for lights...)
--
Shaun.

"Humans will have advanced a long, long way when religious belief has a cozy
little classification in the DSM*."
David Melville (in r.a.s.f1)
(*Diagnostic and Statistical Manual of Mental Disorders)

Sylvia Else
Guest

Thu Nov 30, 2017 10:11 am   



On 29/11/2017 11:21 PM, Peter wrote:
Quote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down with
a CD4020 14 stage ripple counter to give 2Hz at the 14th stage, then I
feed that to the clock pin of a second CD4020. A 1Hz or 1 second clock
"tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter outputs
with simple hardwired diode gates to pick off the exact elapsed times I
want. The only question is whether there could be any problems with
cascading three CD4020's?


You should be able to cascade them indefinitely, even to the point where
the pulse length exceeds the MTBF of the device. Just don't forget to
include enough power decoupling.

Sylvia.

Peter
Guest

Thu Nov 30, 2017 2:06 pm   



On 30/11/2017 5:51 PM, ~misfit~ wrote:
Quote:
Once upon a time on usenet Peter wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down
with a CD4020 14 stage ripple counter to give 2Hz at the 14th stage,
then I feed that to the clock pin of a second CD4020. A 1Hz or 1
second clock "tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter
outputs with simple hardwired diode gates to pick off the exact
elapsed times I want. The only question is whether there could be any
problems with cascading three CD4020's?

I realize this approach is about forty years out of date and it could
probably be done far more elegantly with a single suitably programmed
PIC or similar processor. But I know exactly nothing about PIC
programming and I do have plenty of ripple counters in the parts box.
Peter.

I don't suppose that this helps:
https://youtu.be/bn3uYJrXhhw

(Bigclive talking logic and timers for lights...)

Yes that helped. Only published yesterday too. Thanks! Big Clive is, I
think, quite a clever bloke but he talks to people like me in language I
can understand. Without actually talking down.

Peter
Guest

Thu Nov 30, 2017 2:08 pm   



On 30/11/2017 6:11 PM, Sylvia Else wrote:
Quote:
On 29/11/2017 11:21 PM, Peter wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four hours
and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down
with a CD4020 14 stage ripple counter to give 2Hz at the 14th stage,
then I feed that to the clock pin of a second CD4020. A 1Hz or 1
second clock "tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain to
further divide the time? I know about decoding selected counter
outputs with simple hardwired diode gates to pick off the exact
elapsed times I want. The only question is whether there could be any
problems with cascading three CD4020's?


You should be able to cascade them indefinitely, even to the point where
the pulse length exceeds the MTBF of the device. Just don't forget to
include enough power decoupling.

Sylvia.

So given enough 4020s I could trigger a doomsday device 5000 years
from now? Just have to leave a large enough bank deposit to pay
generations unborn to replace the solar panel every 30 years and the
battery every three years. For 5000 years. Assuming the present
financial system, the thermonuclear doomsday package and humanity last
that long. Puts my little project in perspective.

Computer Nerd Kev
Guest

Thu Nov 30, 2017 11:43 pm   



Jasen Betts <jasen_at_xnet.co.nz> wrote:
Quote:
On 2017-11-29, Computer Nerd Kev <not_at_telling.you.invalid> wrote:

The delay between gates changing state after the clock pulse means
that there will be periods (of a length in the order of microseconds)
where the outputs match the required count in error, because each one
changes before the next.

No, because they are ripple copunters and only count upwards, and
changes (carries) propogate leftwards (by place value) they never will:
all the glitch states are lower than the correct count. ie "missing ones"
and so will never trigger AND logic early


Quite right. The warning I was thinking of was only for the case of
inverted counter outputs.

--
__ __
#_ < |\| |< _#

Computer Nerd Kev
Guest

Thu Nov 30, 2017 11:54 pm   



Peter <noemail_at_pigpond.com> wrote:
Quote:
My "design", if you can call it that, features a hex inverter chip that
will use one gate to take the low at the 24 hour mark and apply a high
to all the reset pins of the counters.


The 4040 is active HIGH and sets all the outputs LOW, so wouldn't this
cause the reset signal to be locked on? To simply reset as soon as 24hrs
is reached, you should be able to connect the HIGH-going output of the
24hrs gate straight to the counter reset inputs.

--
__ __
#_ < |\| |< _#

Computer Nerd Kev
Guest

Fri Dec 01, 2017 12:01 am   



Peter <noemail_at_pigpond.com> wrote:
Quote:
On 30/11/2017 6:11 PM, Sylvia Else wrote:
The only question is whether there could be any
problems with cascading three CD4020's?


You should be able to cascade them indefinitely, even to the point where
the pulse length exceeds the MTBF of the device. Just don't forget to
include enough power decoupling.

So given enough 4020s I could trigger a doomsday device 5000 years
from now? Just have to leave a large enough bank deposit to pay
generations unborn to replace the solar panel every 30 years and the
battery every three years. For 5000 years. Assuming the present
financial system, the thermonuclear doomsday package and humanity last
that long. Puts my little project in perspective.


Sort of like a digital version of this:
https://makezine.com/2012/04/25/arthur-gansons-machine-with-concrete/

--
__ __
#_ < |\| |< _#

Sylvia Else
Guest

Fri Dec 01, 2017 12:10 am   



On 30/11/2017 11:08 PM, Peter wrote:
Quote:
On 30/11/2017 6:11 PM, Sylvia Else wrote:
On 29/11/2017 11:21 PM, Peter wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four
hours and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down
with a CD4020 14 stage ripple counter to give 2Hz at the 14th stage,
then I feed that to the clock pin of a second CD4020. A 1Hz or 1
second clock "tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain
to further divide the time? I know about decoding selected counter
outputs with simple hardwired diode gates to pick off the exact
elapsed times I want. The only question is whether there could be any
problems with cascading three CD4020's?


You should be able to cascade them indefinitely, even to the point
where the pulse length exceeds the MTBF of the device. Just don't
forget to include enough power decoupling.

Sylvia.
So given enough 4020s I could trigger a doomsday device 5000 years
from now?


Yes, except that I suspect the MTBF will get you.

Sylvia

~misfit~
Guest

Fri Dec 01, 2017 4:48 am   



Once upon a time on usenet Peter wrote:
Quote:
On 30/11/2017 5:51 PM, ~misfit~ wrote:
Once upon a time on usenet Peter wrote:
Hello,
Expertise in 4000 series logic family is needed here. I have a timer
application where I need to count to eight hours and twenty four
hours and then reset and start again.
I'm using an Epson crystal clock IC at 32786Hz and dividing it down
with a CD4020 14 stage ripple counter to give 2Hz at the 14th stage,
then I feed that to the clock pin of a second CD4020. A 1Hz or 1
second clock "tick"then appears at the output of the first stage.
The other 13 stages continue dividing until the 14th stage output
finally goes low at something like 2.27 hours after the start.
Is there any reason why I shouldn't add a third CD4020 to the chain
to further divide the time? I know about decoding selected counter
outputs with simple hardwired diode gates to pick off the exact
elapsed times I want. The only question is whether there could be
any problems with cascading three CD4020's?

I realize this approach is about forty years out of date and it
could probably be done far more elegantly with a single suitably
programmed PIC or similar processor. But I know exactly nothing
about PIC programming and I do have plenty of ripple counters in
the parts box. Peter.

I don't suppose that this helps:
https://youtu.be/bn3uYJrXhhw

(Bigclive talking logic and timers for lights...)

Yes that helped. Only published yesterday too. Thanks! Big Clive is, I
think, quite a clever bloke but he talks to people like me in
language I can understand. Without actually talking down.


I'm pleased that it helped.

Yes, agreed. Big Clive is one of the few youtube channels that I subscribe
to that I've enabled notifications for so that I see his videos the day he
uploads them. I watch them all, even if they're not something I'm presently
interested in as he often goes off on tangents and gives good information.
Smile
--
Shaun.

"Humans will have advanced a long, long way when religious belief has a cozy
little classification in the DSM*."
David Melville (in r.a.s.f1)
(*Diagnostic and Statistical Manual of Mental Disorders)

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