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Can you look into your design using an assert statement?

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Volker Kriszeit
Guest

Mon Feb 17, 2020 9:45 pm   



Hi folks,

currently I'm developing a small 2-stage RISC processor. For that, I use
the ALDEC Active-HDL 10.5 simulator to have a look into the design for
debugging purposes. That's working fine, but I want to switch to a VHDL
testbench to automate the validations.

Is there any possibility in the main testbench to get access to signals
deep down in my design when I want to ASSERT some signal? I have asked
google but it always responds with some somewhat trivial syntax
definitions for the ASSERT statement.

Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?

Or am I bound to the top level signals and can't look into the design
using ASSERT? What would be the proper way to do this in a testbench? I
prefer to not alter the design to pass internal signals to the top level
to be able to check them.

TIA

Charles Bailey
Guest

Tue Feb 18, 2020 4:45 am   



On 2020-02-17 14:34, Volker Kriszeit wrote:
Quote:
Hi folks,

currently I'm developing a small 2-stage RISC processor. For that, I use
the ALDEC Active-HDL 10.5 simulator to have a look into the design for
debugging purposes. That's working fine, but I want to switch to a VHDL
testbench to automate the validations.

Is there any possibility in the main testbench to get access to signals
deep down in my design when I want to ASSERT some signal? I have asked
google but it always responds with some somewhat trivial syntax
definitions for the ASSERT statement.

Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?

Or am I bound to the top level signals and can't look into the design
using ASSERT? What would be the proper way to do this in a testbench? I
prefer to not alter the design to pass internal signals to the top level
to be able to check them.

TIA

I think your best best would be to put the ASSERT statement in the VHDL
entity/architecture where the signal exists. ASSERT statements are
ignored by synthesis tools.

I'm not familiar with ALDEC Active-HDL but most commercial simulators
have the capability to put a watch on any signal in the design using the
simulator's scripting language, such as TCL. You can have simulator
take some action, such as printing out a message, when the signal meets
some test condition. So, that would be another approach.

Charles Bailey

Thomas Stanka
Guest

Tue Feb 18, 2020 3:45 pm   



Hello,

Am Montag, 17. Februar 2020 21:34:19 UTC+1 schrieb Volker Kriszeit:
Quote:
Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?


VHDL 2008 provides a mechanisms to access hierarchy. This allows something like

ALIAS internalReadport << MyProcessor.HazardDetectionUnit.readPortAOp >>;
...
ASSERT internalReadport='1'....


Additionally ALDEC has similar to Modelsim a propritary mechanism to access signals inside, see the documentation of ALDEC for details, but be aware that this mechanism is simulator dependend and therefore not valid VHDL.

regards,

Thomas

Volker Kriszeit
Guest

Tue Feb 18, 2020 5:45 pm   



In article <r2fm6j$jln$1_at_dont-email.me>, logicguy76_at_gmail.com says...

Quote:
I think your best best would be to put the ASSERT statement in the VHDL
entity/architecture where the signal exists. ASSERT statements are
ignored by synthesis tools.

I'm not familiar with ALDEC Active-HDL but most commercial simulators
have the capability to put a watch on any signal in the design using the
simulator's scripting language, such as TCL. You can have simulator
take some action, such as printing out a message, when the signal meets
some test condition. So, that would be another approach.

Charles Bailey


Hi Charles,

I'm defintely going to try this, if the suggestion Thomas made (using
VHDL-2008 ALIAS statement) doesn't work for me.

Thanks & best regards,
Volker

Volker Kriszeit
Guest

Tue Feb 18, 2020 5:45 pm   



In article <139c7db4-8528-4642-bb57-d99936c56a45_at_googlegroups.com>,
usenet_nospam_valid_at_stanka-web.de says...
Quote:

Hello,

Am Montag, 17. Februar 2020 21:34:19 UTC+1 schrieb Volker Kriszeit:
Is there something like
ASSERT (MyProcessor.HazardDetectionUnit.readPortAOp = '1') report
"readPortAOp in the hazard detection unit is not set" SEVERITY FAILURE
in VHDL?

VHDL 2008 provides a mechanisms to access hierarchy. This allows something like

ALIAS internalReadport << MyProcessor.HazardDetectionUnit.readPortAOp >>;
..
ASSERT internalReadport='1'....


Additionally ALDEC has similar to Modelsim a propritary mechanism to access signals inside, see the documentation of ALDEC for details, but be aware that this mechanism is simulator dependend and therefore not valid VHDL.

regards,

Thomas


Hello Thomas,

thank you for your suggestion! I'm going to try the VHDL-2008 ALIAS
statement. Looks good, seems to be exactly what I need.

If that doesn't work, I'll dive into the depths of the simulator.

regards,

Volker


Guest

Wed Feb 19, 2020 2:45 am   



Volker wrote:
Quote:

I'm defintely going to try this, if the suggestion Thomas made (using
VHDL-2008 ALIAS statement) doesn't work for me.

Another option for pre-2008 VHDL signal monitoring, without using vendor specific simulator extensions, is to put a copy of the signals needing to be traced into a package, where they can then be driven from the appropriate level of the hierarchy.


I used this approach to provide the simulator trace dumps for my own homebrew RISC verification test bench many years ago, code examples here:

https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe_pkg.vhd
https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe.vhd

-Brian

Volker Kriszeit
Guest

Fri Feb 21, 2020 9:45 pm   



In article <60c6e063-5e93-4f26-88a6-9d09121979b7_at_googlegroups.com>,
brimdavis_at_gmail.com says...

Quote:
Another option for pre-2008 VHDL signal monitoring, without using vendor specific simulator extensions, is to put a copy of the signals needing to be traced into a package, where they can then be driven from the appropriate level of the hierarchy.

I used this approach to provide the simulator trace dumps for my own homebrew RISC verification test bench many years ago, code examples here:

https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe_pkg.vhd
https://github.com/brimdavis/yard-1/blob/master/hdl/cores/y1a/y1a_probe.vhd

-Brian


Thanks, Brian!

I'll try this once my design gets bigger. For the time being I decided
to use the VHDL-2008 ALIAS statement, as Thomas suggested. This works
very well for me.

Regards,
Volker

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