# Can you help me solve this Verilog problem ?

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Amartya Saikia
Guest

Mon Nov 05, 2018 3:45 pm

1.Design the required circuit(s) for the following
Input: two 4-bit numbers

a.) If a code ‘01’ is selected two numbers will be added.
b.) If a code ‘10’ is selected XOR operation will be performed on the two numbers.
c.) If a code ‘11’ is selected both the numbers become zero.. (0000, 0000)

2. Write the required Verilog code to implement the above.

I am a Chemical Major and was given to solve this, I have no prior experience and due to unjust rules, I have to submit it within a few days. Can you help me solve it?

Kevin Neilson
Guest

Mon Nov 05, 2018 6:45 pm

On Monday, November 5, 2018 at 7:34:19 AM UTC-7, Amartya Saikia wrote:
Quote:
1.Design the required circuit(s) for the following
Input: two 4-bit numbers

a.) If a code ‘01’ is selected two numbers will be added.
b.) If a code ‘10’ is selected XOR operation will be performed on the two numbers.
c.) If a code ‘11’ is selected both the numbers become zero. (0000, 0000)

2. Write the required Verilog code to implement the above.

I am a Chemical Major and was given to solve this, I have no prior experience and due to unjust rules, I have to submit it within a few days. Can you help me solve it?

A few days is sufficient time for you to solve this problem.

Johann Klammer
Guest

Tue Nov 06, 2018 5:45 am

On 11/05/2018 03:34 PM, Amartya Saikia wrote:
Quote:
1.Design the required circuit(s) for the following
Input: two 4-bit numbers

a.) If a code ‘01’ is selected two numbers will be added.
b.) If a code ‘10’ is selected XOR operation will be performed on the two numbers.
c.) If a code ‘11’ is selected both the numbers become zero. (0000, 0000)

2. Write the required Verilog code to implement the above.

I am a Chemical Major and was given to solve this, I have no prior experience and due to unjust rules, I have to submit it within a few days. Can you help me solve it?

module blabla(input wire [1:0]code,input wire [7:0]a,input wire [7:0]b,output wire [7:0]a_out,output wire [7:0]b_out)

always @*
case(code)
2'b01:
begin
a_out=a+b;
b_out=b;
end
2'b10:
begin
a_out=a^b;
b_out=b;
end
default:
begin
a_out=0;
b_out=0;
end
endcase
endmodule

Amartya Saikia
Guest

Tue Nov 06, 2018 10:45 am

Thank You Johann Klammer, I tried executing and followed the log. It led me to conclusion that, while using an "always block", the data output needs to be a register type and not a wire. [link](https://electronics.stackexchange.com/questions/321125/why-need-to-declare-output-as-a-register-in-verilog)

So should the code be modified to:

module coa
(input [1:0] code,
input [7:0] a,
input [7:0] b,
output reg [7:0] a_out,
output reg [7:0] b_out);

Also, I read today that, if we don't specify anything, the variable is assumed to be wire. So, is the input variable a wire. How should I handle the inputs? Thank You so much for helping me out.

Johann Klammer
Guest

Tue Nov 06, 2018 12:45 pm

On 11/06/2018 12:05 PM, Amartya Saikia wrote:
Quote:
Do you have a personal favorite Verilog simulator? I am new. Also, any extra suggestion?

Are there any others besides icarus verilog?
No, I have no other suggestions...(but I don't write much verilog either)

Amartya Saikia
Guest

Tue Nov 06, 2018 12:45 pm

OK got it. Thank You so much. I am getting the idea on how to approach such problems. I will ask my Prof about '00' and make it work around accordingly. We are not taught Verilog but are asked to try and solve it. I am learning it now and the community is very helpful. Thank You so much.

Do you have a personal favorite Verilog simulator? I am new. Also, any extra suggestion?

Johann Klammer
Guest

Tue Nov 06, 2018 12:45 pm

On 11/06/2018 09:56 AM, Amartya Saikia wrote:
Quote:
Thank You Johann Klammer, I tried executing and followed the log. It led me to conclusion that, while using an "always block", the data output needs to be a register type and not a wire. [link](https://electronics.stackexchange.com/questions/321125/why-need-to-declare-output-as-a-register-in-verilog)

So should the code be modified to:

module coa
(input [1:0] code,
input [7:0] a,
input [7:0] b,
output reg [7:0] a_out,
output reg [7:0] b_out);

Also, I read today that, if we don't specify anything, the variable is assumed to be wire. So, is the input variable a wire. How should I handle the inputs? Thank You so much for helping me out.

(I did not try to compile it)
Yes. use wire for the inputs, reg for the output. you can use wire for the outputs if you manage to write the
whole thing as a combinatorial assignments, but the always block is more readable.
Just remember to always assign all the variables to avoid latches and @* for combinatorial output.

There's still the question what should happen for code==2'b00 ?
Here it does the same as 2'b11.

Depending on what you professor actually wants there might be registers needed and clk and rst.

Johann Klammer
Guest

Tue Nov 06, 2018 12:45 pm

On 11/06/2018 12:05 PM, Amartya Saikia wrote:
Quote:
Also, any extra suggestion?

You can try to look for these pdfs(just google):

Standard Gotchas
Subtleties in the Verilog and SystemVerilog Standards That
Every Engineer Should Know
Stuart Sutherland
Sutherland HDL, Inc.
stuart_at_sutherland-hdl.com
Don Mills
Microchip Technology
don.mills_at_microchip.com

Gotcha Again
More Subtleties in the Verilog and SystemVerilog Standards
That Every Engineer Should Know
Stuart Sutherland
Sutherland HDL, Inc.
stuart_at_sutherland-hdl.com
Don Mills
LCDM Engineering
mills_at_lcdm-eng.com
Chris Spear
Synopsys, Inc.
chris.spear_at_synopsys.com

Nonblocking Assignments in Verilog Synthesis, Coding
Styles That Kill!
Clifford E. Cummings
Sunburst Design, Inc.
cliffc_at_sunburst-design.com
www.sunburst-design.com

Johann Klammer
Guest

Tue Nov 06, 2018 12:45 pm

On 11/06/2018 12:05 PM, Amartya Saikia wrote:
Quote:
OK got it. Thank You so much. I am getting the idea on how to approach such problems. I will ask my Prof about '00' and make it work around accordingly. We are not taught Verilog but are asked to try and solve it. I am learning it now and the community is very helpful. Thank You so much.

Do you have a personal favorite Verilog simulator? I am new. Also, any extra suggestion?

I also got the bit widths wr0ng. should be:
(input [1:0] code,
input [3:0] a,
input [3:0] b,
output reg [3:0] a_out,
output reg [3:0] b_out);

and you may want a carry bit for that add..
or
output reg [4:0] a_out,
or something

Amartya Saikia
Guest

Tue Nov 06, 2018 2:45 pm

Ok, sure. Thank You. Will look for the resources.

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