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Can I use Verilog or SystemVerilog to write a state machine

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Weng Tianxiang
Guest

Wed Jan 09, 2019 2:45 am   



Hi Kevin,

1. No source code is provided for a testing bench except demonstrating my ideas.

Then anything using your invention...
2. "-Will use additional logic."
No additional logic is used except a clock gating device.

3. " The power consumed by that logic will have to be subtracted out from whatever power savings might get realized from clocking less frequently. "
No additional power is consumed on no additional logic.

4. "-Will be impossible to get timing closure in an FPGA environment"
Wrong! Xilinx has a built-in clock enable input for 8 register in a LUT6 block.

5. "-Will consume more power in an FPGA."
Wrong!

6. "TBD if it will in an ASIC." I don't know what "TBD" stands for.

7. "-Will not end up saving much power since state machine consume a relatively small portion of the power"
It is right if for a single state machine, but not correct when dealing with 100,000 state machines.

8. I just mentioned that skipping a cycle pulse would save power. No more than that is mentioned. It is not my business.

Thank you.

Weng

Richard Damon
Guest

Wed Jan 09, 2019 4:45 am   



On 1/6/19 8:59 PM, Weng Tianxiang wrote:
Quote:
I want to use my method in all types of circuits. A clock gating device is basically a latch. A FF with a clock enable input is a FF having a latch. Thank you.


Unless you are using the term different than I am used to I would
disagree somewhat.

A "latch" is, to my language, and asynchronous memory unit that copies
it input to its output for one level of the enable, and the output holds
its current value for the other level of the enable. It is one of the
more primitive memory unit.

A latch could be used for clock gating, but is highly inefficient for
doing so, as the properly designed clock gate knows what state the
output should be in the gated off state, so doesn't need to the logic to
maintain current state. The clock gating device is basically a GATE.

There may be a way to use a latch to build a gated ff, but again, there
are simpler methods with better timing.

KJ
Guest

Wed Jan 09, 2019 4:45 am   



On Tuesday, January 8, 2019 at 8:04:01 PM UTC-5, Weng Tianxiang wrote:
Quote:
Hi Kevin,

1. No source code is provided for a testing bench except demonstrating my ideas.


You stated in an earlier post "In my invention there is no one single logic gate generated for comparison "WState /= WState_NS". Is it obvious to you?" but the code being referenced was not from a gated clock design so there is nothing 'demonstrating your idea' whatever that may be.

Quote:

Then anything using your invention...
2. "-Will use additional logic."
No additional logic is used except a clock gating device.

Did you not even notice your use of the word 'except' after you typed it?


No matter. So this 'clock gating device', either has only one input (which is the only thing that would not require logic resource to implement) or it has more than one input and can generate the correct gated clock output without any logic resources, which means it works by magic. The absurdity meter is pegged at the highest setting with this claim of yours.

Quote:
3. " The power consumed by that logic will have to be subtracted out from whatever power savings might get realized from clocking less frequently. "
No additional power is consumed on no additional logic.

Well of course. Why would the 'operates by magic' clock gating device which is only needed with your "invention" require any power in order to operate? Absurdity meter has gone off scale.


Quote:
4. "-Will be impossible to get timing closure in an FPGA environment"
Wrong! Xilinx has a built-in clock enable input for 8 register in a LUT6 block.

You've been told this before by others, but a clock enable input is not the same thing as a gated clock. Specifically, in typical electrical engineering parlance, a 'clock enable' signal modifies the data input to a flip flop, not the clock input. 'Clock enable' signals do not modify the clock in any way. Do some more research, this is a pretty basic logic design concept.


Quote:
5. "-Will consume more power in an FPGA."
Wrong!

I am correct and I sent you the full details back in 2010. The governing NDA for that work is no longer in force but I won't post all the details here that back my claim in order to avoid embarrassing you any further. If you would like to post your actual design, methods and measurements here to provide evidence to justify your stance, feel free. Simply making statements and claims is not evidence.


Quote:
6. "TBD if it will in an ASIC." I don't know what "TBD" stands for.

You seem to have a lot of outages of Google at your place.


Quote:
7. "-Will not end up saving much power since state machine consume a relatively small portion of the power"
It is right if for a single state machine, but not correct when dealing with 100,000 state machines.

No, the number of state machines does not matter since they will (or should) be controlling much larger stuff that would consume the bulk of the power.. If you have 100,000 state machines controlling 10,000 things in a data path, you likely have incompetently designed state machines.


Quote:
8. I just mentioned that skipping a cycle pulse would save power. No more than that is mentioned. It is not my business.

Yes, you stated that but can provide no evidence to back that claim. Without that, you're just making unfounded statements, many of which are clearly incorrect and have been pointed out to you...for many years now.


Kevin Jennings

Weng Tianxiang
Guest

Wed Jan 09, 2019 6:45 am   



Hi Richard,

I don't think so:
"The clock gating device is basically a GATE"!

Kevin,
"No, the number of state machines does not matter since they will (or should) be controlling much larger stuff that would consume the bulk of the power. If you have 100,000 state machines controlling 10,000 things in a data path, you likely have incompetently designed state machines. "

One state machine controls the status for a 64 bytes L2 cache line, and 100,000 state machines fully control 6M L2 cache status. It does not control data path! Their states will be affect how each of L2 cache line behaves.

If you have time have a look at the following 2 patents, at least you can understand what each of those 1000,000 state machines is and and how it works.

Thank you.

Weng

Weng Tianxiang
Guest

Wed Jan 09, 2019 6:45 am   



Hi Kevin,

I thank you for your help many years ago.

It is not correct:
"a 'clock enable' signal modifies the data input to a flip flop, not the clock input. 'Clock enable' signals do not modify the clock in any way."

When a CLOCK ENABLE is deasserted, no clock pulse will feed a FF, and the FF will keep unchanged on the next cycle. If a CLOCK ENABLE is asserted, a clock pulse will feed a FF, and the FF will be updated on the next cycle.

Thank you.

Weng

Weng Tianxiang
Guest

Wed Jan 09, 2019 7:45 am   



Hi Richard and Kevin,

Here is a copy from Wikipedia "clock gating":
https://en.wikipedia.org/wiki/Clock_gating

Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree. Pruning the clock disables portions of the circuitry so that the flip-flops in them do not have to switch states. Switching states consumes power. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred..[1]

Clock gating works by taking the enable conditions attached to registers, and uses them to gate the clocks. A design must contain these enable conditions in order to use and benefit from clock gating. This clock gating process can also save significant die area as well as power, since it removes large numbers of muxes and replaces them with clock gating logic. This clock gating logic is generally in the form of "integrated clock gating" (ICG) cells. However, the clock gating logic will change the clock tree structure, since the clock gating logic will sit in the clock tree.

Clock gating logic can be added into a design in a variety of ways:

Coded into the register transfer level (RTL) code as enable conditions that can be automatically translated into clock gating logic by synthesis tools (fine grain clock gating).

Inserted into the design manually by the RTL designers (typically as module level clock gating) by instantiating library specific integrated clock gating (ICG) cells to gate the clocks of specific modules or registers.
Semi-automatically inserted into the RTL by automated clock gating tools. These tools either insert ICG cells into the RTL, or add enable conditions into the RTL code. These typically also offer sequential clock gating optimisations.

Any RTL modifications to improve clock gating will result in functional changes to the design (since the registers will now hold different values) which need to be verified.

Sequential clock gating is the process of extracting/propagating the enable conditions to the upstream/downstream sequential elements, so that additional registers can be clock gated.

Although asynchronous circuits by definition do not have a "clock", the term perfect clock gating is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry. As the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit: the circuit only generates logic transitions when it is actively computing.[2]

Chip intended to run on batteries or with very low power such as those used in the mobile phones, wearable devices, etc. would implement several forms of clock gating together. At one end is the manual gating of clocks by software, where a driver enables or disables the various clocks used by a given idle controller. On the other end is automatic clock gating, where the hardware can be told to detect whether there's any work to do, and turn off a given clock if it is not needed. These forms interact with each other and may be part of the same enable tree. For example, an internal bridge or bus might use automatic gating so that it is gated off until the CPU or a DMA engine needs to use it, while several of the peripherals on that bus might be permanently gated off if they are unused on that board.

Weng

Jan Coombs
Guest

Wed Jan 09, 2019 12:45 pm   



On Tue, 8 Jan 2019 21:10:58 -0800 (PST)
Weng Tianxiang <wtxwtx_at_gmail.com> wrote:

Quote:
It is not correct:
"a 'clock enable' signal modifies the data input to a flip flop, not the clock input. 'Clock enable' signals do not modify the clock in any way."


I heard long ago that the 'clock enable' signal in Xilinx
FPGAs does not affect the clock signal. This is likely to allow
sharing clock edge detection, and to minimise the routing to a
block of flops with shared clock signal. Patent here [1].

> When a CLOCK ENABLE is deasserted, no clock pulse will feed a FF, and the FF will keep unchanged on the next cycle. If a CLOCK ENABLE is asserted, a clock pulse will feed a FF, and the FF will be updated on the next cycle.

This is from a logic user's guide, with simplified explanation
based on the implementation of a single flip-flop, and is not
intended to be a circuit description.

Suggestion: 'The hardest thing to know is (the extent of) what
we do not know.'

Quote:
Thank you.

Weng


Jan Coombs
--

[1] Clock enable control circuit for flip flops
United States Patent 6466049 [2002]
http://www.freepatentsonline.com/6466049.html

john
Guest

Wed Jan 09, 2019 1:45 pm   



In article <20190109105441.5be0a472_at_t530>,
jenfhaomndgfwutc_at_murmic.plus.com says...
Quote:

I heard long ago that the 'clock enable' signal in Xilinx
FPGAs does not affect the clock signal. This is likely to allow
sharing clock edge detection, and to minimise the routing to a
block of flops with shared clock signal. Patent here [1].


Xilinx recommends clock gating be fed through bufgce to prevent skew
and timing issues (you also gain good fanout of course) if feeding large
enough numbers of blocks.,
Vivado automatcaly moves the gating to the enable path for flip flops
or latches (can be manually overriden though I've not done that yet)

As for writing patents based on other peoples patents - this thread confirms
the obvious:

To quote Daniel Whitehall:
"Discovery requires experimentation"
Marvels agents of SHIELD

john

=========================
http://johntech.co.uk
=========================

Thomas Stanka
Guest

Wed Jan 09, 2019 1:45 pm   



Am Mittwoch, 9. Januar 2019 06:31:03 UTC+1 schrieb Weng Tianxiang:
Quote:
Hi Kevin,

I thank you for your help many years ago.

It is not correct:
"a 'clock enable' signal modifies the data input to a flip flop, not the clock input. 'Clock enable' signals do not modify the clock in any way."

When a CLOCK ENABLE is deasserted, no clock pulse will feed a FF, and the FF will keep unchanged on the next cycle. If a CLOCK ENABLE is asserted, a clock pulse will feed a FF, and the FF will be updated on the next cycle.


In theory a "clock enable" gates the clock line, but in reality it usually switches only the data path to the FF.
In most technologies the enable of a FF with Clock enable is synchronous used.
If you zoom into a typical clock enable-FF you will find the following hardware implemented.
(use fixed font for view)

_________________________
| |
| +---+ +-------+ |
--| | | | |
|MUX|---|D Q|-----------
D ----| | | |
+---+ | FF |
| | |
Enable------- | |
| |
Clock ___________|\ |
|/ |
+-------+

A clock tree is the tree of buffer (inverter) between clock source and each FF and the gating is often performed on a dedicated branch of the clock tree which is no leaf.
It is ofc possible and most flexible to gate the clock direct before the FF (and therefore at the end of the leaf) but this has the least power saving effect and the worst impact in resource usage.
The best effect is gained when gating as near as possible on to the clock source.
On the other hand this is not trivial as the clock tree without any clock gate would connect maybe 8 FF that are functional close together on same leaf of the clock tree but if of these 8 FF only one should be gated than you need to move the gating FF from non gated branch to a gated branch which might connect this FF to some other FF that are pyhsically located further away increasing routing effort and routing delay.

In many cases the power consumption of the clock tree switching with clock gating only on the FF itself is not smaller than the power consumption of the same tree with synchronous data gating as the FF itself is in both implementations keeping its outputs constant when "gated" and the load of the FF located clock gate is same as the load of the FF.

The synchronous enable has from timing point of view a strong advantage vs clock gating and is therefore easier to handle in layout.

regards,

Thomas

KJ
Guest

Wed Jan 09, 2019 3:45 pm   



On Tuesday, January 8, 2019 at 6:23:40 PM UTC-5, Weng Tianxiang wrote:
Quote:
Kevin,

In my invention, all state machines will be synthesized to have clock gating function, no matter whether or not it is coded to have clock gating device!

Then your invention will optimally use the toggle flip flop as the fundamental storage device. There are several flavors of basic flip flops: SR (set-reset), JK (improved set-reset), T (toggle) and D. The industry has long since settled on using essentially only the D type and presumably has optimized that one. So to use your invention one would have to either use a non-optimal flip flop or construct it from the D type, which presumably would be less optimal than if it were a true T type.


If the industry had settled on using only T flip flops then we would all be doing gated clock designs now. But just because it hasn't does not mean that the T flip flop and the associated gated clock logic required to use that flip flop type is not already existing prior art. It is simply prior art that is not widely used. A single logic description can be synthesized to use any of the basic flip flop types inherent in the underlying hardware. So the mapping of some VHDL/Verilog source code to be implemented using T flip flops as storage is not novel.

While nearly every invention is a new novel use that builds on prior art your apparent claim here "all state machines will be synthesized to have clock gating function" is nothing more than stating that "all state machines will be synthesized using T flip flops" which is neither new nor novel. The limitation to "all state machines" rather than "all memory storage" is a restriction over what is already existing so that is not novel either.

Kevin Jennings

Weng Tianxiang
Guest

Wed Jan 09, 2019 5:45 pm   



Hi,
Thank you for more people involved in this discussion.

1. Here is my prior art description of FIG. 1 on how a clock gating device is used. Clock gating device is used in my invention as a prior art device.

[0009] FIG. 1 is an interface diagram for any type of clock gating device currently known in the art. These types of clock gating devices have their clock input ‘>’ coupled to a state machine’s clock source, with its clock pulse output C driving a clock pulse on the next cycle if the clock enable input E is asserted on the current cycle.

2. Because of the strict requirement of IEEE Transaction requirement on paper's originality, I cannot disclose any details of my invention until about 3 months later. The paper contains 11 double column pages, excluding the author's biography, and 10 related schematic diagrams of related state machine's circuits.

From the schematic diagrams you can immediately know that the full circuit of a state machine is much simpler than any counterpart of a conventional state machine circuit with clock enable logic naturally generated without any extra logic.

Thank you.

Weng

KJ
Guest

Wed Jan 09, 2019 7:45 pm   



On Wednesday, January 9, 2019 at 11:44:56 AM UTC-5, Weng Tianxiang wrote:
Quote:

From the schematic diagrams you can immediately know that the full circuit of a state machine is much simpler than any counterpart of a conventional state machine circuit with clock enable logic naturally generated without any extra logic.

The schematic of a ripple counter implemented with T flip flops is also quite simple when compared to that of a conventional synchronous counter. As I previously posted, use of T flip flops rather than D flip flops (and the consequential generation of gated clocks to support synthesis using T flip flops) is existing prior art that is covered in old textbooks. Your chosen subset of use cases such as state machines is a restriction over what is already out as prior art which covered all synchronous machines.


Kevin Jennings

Weng Tianxiang
Guest

Wed Jan 09, 2019 8:45 pm   



“Your chosen subset of use cases such as state machines is a restriction over what is already out as prior art which covered all synchronous machines. ”

My method only applies to a state machine circuit and defines many brand new concepts for a state machine.

The method is useless for FPGA as nobody cares about a low power state machine circuit. The saver of my invention is the case of CPU' 100,000 state machines for 6M L2 cache.

Weng

gtwrek
Guest

Wed Jan 09, 2019 9:45 pm   



In article <3913d54c-b09e-4a4d-8890-3359a13ba7ea_at_googlegroups.com>,
Weng Tianxiang <wtxwtx_at_gmail.com> wrote:
Quote:
“Your chosen subset of use cases such as state machines is a restriction over what is already out as prior art which covered all synchronous machines. ”

My method only applies to a state machine circuit and defines many brand new concepts for a state machine.

The method is useless for FPGA as nobody cares about a low power state machine circuit. The saver of my invention is the case of CPU' 100,000 state machines
for 6M L2 cache.


Sigh, can't believe I keep letting myself get dragged into these
discussions...

Weng - what you're completely missing what many have been telling you -
your definition of a "state machine" is so broad that it's essentially
meaningless. Since you think that YOUR definition of a "state machine"
includes this 6M L2 cache, then as Ken and I have tried to tell you,
your "state machine" definition includes the subset of ALL synchronous
machines.

This isn't a terrible definition of a state machine, (but one that
doesn't offer much utility). But this just goes to show you that any
Super Snazzy Ideas you've got have already been shown in prior art, in
the general set of all synchronous machines, as Ken's trying to
communicate to you.

I fear you'll ignore this information as you've ignored most of what
information others have tried to communicate to your in the past (in
this thread and others). But I'm saying it anyway.

I'll await your reply with more sets of patent result hits from
google... Wink <- Sarcasm

Regards,

Mark

gtwrek
Guest

Wed Jan 09, 2019 9:45 pm   



In article <q15k3l$g4j$1_at_dont-email.me>, gtwrek <gtwrek_at_sonic.net> wrote:
> Many attributions to "Ken" that should have attributed "Kevin"

Sorry Kevin for the misattribution...

Regards,

Mark

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