Byte stuffing while getting constant bytes input

Thu Jun 24, 2010 11:29 pm   

I'm in the process of putting a version of the KISS protocol into a
module in VHDL.
It works like this.

1. Whenever a signal called Active goes high and I insert a Start
character (say, x"7D") into my FIFO as the first byte.

2. Whenever Active goes low and I insert a stop character (say x"5D")
into my stream at the end.

3. While active is high, if I see the start, stop or escape characters
in my stream, I do two things (a) insert the escape character into the
stream, (b) follow that by the complement of the start, stop or escape
byte. This requires inserting an extra byte into the stream.

The problem I am having is I am writing these to a FIFO and if I have
a constant stream of bytes to write on every clock cycle and I see an
one of the KISS bytes (stop, start or escape character) in my stream,
how do I handle writing all these bytes into the FIFO because I seem
to lose a byte that is being pulsed in because I am writing the ESC
and complement bytes into the FIFO.

If have pasted my code snippet of the FIFO and state machine that
writes into it below:




------------

Type KissStateType Is ( KissIdle, GotStart, SntEsc);
signal KissState : KissStateType;


signal TxDataQ : std_logic_vector(7 downto 0);
signal TxEmpty_int : std_logic;
signal rd_en : std_logic;
signal FifoWr : std_logic;
signal esc_ctrl : boolean;
signal FifoDataIn, TxBuff : std_logic_vector(7 downto 0);
signal Active_reg : std_logic;

component lvdm_tx_fifo_8x16
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;

begin

U_lvmd_tx_fifo1 : lvdm_tx_fifo_8x16
port map (
rst => reset,
din => FifoDataIn,
wr_clk => TxInClk,
wr_en => FifoWr,
rd_clk => TxOutClk,
rd_en => rd_en,
dout => TxDataQ,
empty => TxEmpty_int,
full => TxFull);


esc_ctrl <= true when TxData = KISS_START else
true when TxData = KISS_END else
true when TxData = KISS_ESC else
false;

KISS_Proto:
process ( Reset, TxInClk )
begin
if Reset = '1' then
Active_reg <= '0';
FifoDataIn <= X"00";
FifoWr <= '0';
KissState <= KissIdle;
TxBuff <= X"00";
elsif Rising_Edge (TxInClk) then
Active_Reg <= Active;
FifoWr <= '0';
case KissState is
when KissIdle =>
if Active_reg = '0' and Active = '1' and TxPulse
then
FifoDataIn <= KISS_START;
TxBuff <= TxData;
FifoWr <= '1';
KissState <= GotStart;
else
KissState <= KissIdle;
end if;


-------------
Salman

Thu Jun 24, 2010 11:29 pm   

On Thu, 24 Jun 2010 13:29:35 -0700 (PDT), Abu Saliha
<salmanisheikh_at_gmail.com> wrote:


[escape-stuffing protocol]


Two possibilities I can see easily:
1) Use DLL/PLL etc to get a clock at 2x the data frequency.
Use that clock to do the FIFO writing. It's then fairly
straightforward to insert the escapes when needed, and
just idle for alternate fast clock cycles most of the time.

2) Make the FIFO one bit wider (dead easy in most FPGAs, which
generally have 9-bit memory). At the input side of the FIFO,
don't do any byte stuffing but instead just set the extra bit
to '1' for bytes that need to be stuffed. Do the stuffing
at the output end of the FIFO.

The best choice probably depends on the details of what's
happening on the output side of the FIFO. I guess that's
feeding some kind of serializer? What's the clock rate
for the serializer?
--
Jonathan Bromley

Fri Jun 25, 2010 12:20 am   

On Jun 24, 4:43 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:


Approach one won't work as we don't want to use more PLLs than
necessary as this is for a spaceflight design on a SpaceGrade Virtex-4-
QV.
I will try approach 2. Its a USART that runs at a 62MHz input rate and
output at 10Mhz. Thanks.

Salman