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Danny
Guest

Wed Sep 03, 2003 12:49 pm   



Hi all,

It is nice that I can find a newsgroup about electronics testing. I am
currently a new graduate from University and is currently working in a
Test Engineering department of a factory. A few questions have came to
me recently and I hope you people can give me a hand.

1)
What is a boundary scan TEST?

2)
Our department is using 2 way of testing. One of them is called ICT
machine and the other one is called PIN JIG (ATE). It is a jig with
heaps of pins on. Then a circuit board is on top of the pin jig. This
pin jig is also connected to a PC and the test program in PC will do
the testing. They call it FUNCTIONAL TEST. I would like to know what
are the differences between functional test (pin jig test) and ICT
test?

3)
Are the 2 test methods belong to a BOUNDARY SCAN TEST?

4)
I have scanned through a research paper about "Implementation of
boundary scan in VHDL". Is it mean a functional test can be implement
in FPGA and what are their advantages?

Thank you for your help!!

From: Danny

Todd H.
Guest

Sat Sep 20, 2003 2:28 am   



hmak003_at_yahoo.com (Danny) writes:
Quote:
Hi all,

It is nice that I can find a newsgroup about electronics testing. I am
currently a new graduate from University and is currently working in a
Test Engineering department of a factory. A few questions have came to
me recently and I hope you people can give me a hand.

1)
What is a boundary scan TEST?

I was a fast static RAM memory chip designer in my former life. I'll
give you my view of it, as I worked on a part where we were
implementing JTAG/boundary scan on chip that was to be packaged in a
119-ball PBGA (plastic ball grid array) package.

Caveat: boundary scan test probably means many many different things
to different people. This is just my view as someone who designed a
full custom memory chip over 6 years ago that had to implement it. At
the time I didn't even know wht the hell a state machine was because I
was such a full-custom transistor-level design guy who'd never worked
on a logic-intensive chip of any sort.

Boundar scan... is a means by which all the pads of the chip were
connected together logically, each with it's own little register.
There was a scan in and scan out pad and maybe a control pad if memory
served. It was a way that a serial trace along the circuit board of
say a motherboard couuld snake through from chip to chip--and with
just this one little serial line, you could load up all the chips on
the board with values into the registers of all the chip pads on all
chips on the board and do something of a system test from that state.

On the chip, the boundary scan logic had a little state machine that
you could push into various modes to do various things that you could
absolutely not do without having more invasive access and more traces
on teh motherboard.

There is an IEEE standard on how the state machine needs to work, so
that all chips sorta talk about boundary scan the same way. Do a
search on JTAG...joint test blah group or something.

As it was explained to me, this whole thing came about as a way to
facilitate board level testing when these flip chip packages came in
and suddenly made it damned hard to clip a probe lead onto any given
chip input (since in pbga packages, the solder balls are completely
inaccessible unlike, say an SOIC or DIP package).


This boundary scan stuff gives test engineers a way to see inside that
sealed chip package and verify board level connectivity among other
things.


Quote:
2)
Our department is using 2 way of testing. One of them is called ICT
machine and the other one is called PIN JIG (ATE). It is a jig with
heaps of pins on. Then a circuit board is on top of the pin jig. This
pin jig is also connected to a PC and the test program in PC will do
the testing. They call it FUNCTIONAL TEST. I would like to know what
are the differences between functional test (pin jig test) and ICT
test?

3)
Are the 2 test methods belong to a BOUNDARY SCAN TEST?

4)
I have scanned through a research paper about "Implementation of
boundary scan in VHDL". Is it mean a functional test can be implement
in FPGA and what are their advantages?

Boundary scan is an enabling technology that can allow you to do many
things. You don't mention in your post what it is you're attempting
to do, so it's really hard to say. The research paper may be
describing to potential designers of chips: "hey you gotta include
boundary scan in your ASIC? Well have I got some VHDL you can reuse
that when synthesized will give you a nice set of logic gates to plop
down onto your chip so you can go have a beer instead of manually
designing all that crap at the gate level."

VHDL isn't just for burning FPGA's -- it's also a way to synthesize
down to placeable layout for implementation in an ASIC design, or even
a full-custom chip design such as a CPU or logic-intensive memory, or
some such.

Best Regards,
--
Todd H.
http://www.toddh.net/

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