Board layout for FPGA

Thu Feb 04, 2010 8:22 am   

Hi guys.. I'm getting ready to start working on my first board layout
with a BGA package (FG456). First will be a prototype for sure.
I was just wondering a few things...

Probably the critical part of my design will be interface to a few
asynchronous SRAMs.

In a relatively low speed design (buses at 10-25MHz) do I need to
worry about things like termination and trace length on the RAM buses?
Should I dedicate address/data pins to each chip in a shared memory
space, or is it better to daisy chain them on a bus? (It seems to me
that routing will be a little easier if each chip gets its own
lines..)

If I won't be using the innermost IO pins, can I get away with a 4-
layer design, two signal layers and power/ground?

Looking at a Xilinx app note with a suggested escape route for this
package, they have three signal layers with 5 mil width traces, the
third of which I believe I can do without...
And lastly, I guess that I will be needing 1.8 and 2.5V supplies, as
well as 3.3V for all of my I/O supplies.. should these all be routed
in the dedicated power layer? If the layer is mostly covered a plane,
which voltage is supposed to be the plane? 3.3V?

And lastly, when connecting I/Os, is there any sensible approach? My
tendency is to want to choose the I/Os so that everything lines up
nicely, but I find it to be a hassle in this case, that in Eagle we
have to connect nets in the schematic first and can't back-annotate
from the board.

Anything else I should be worrying about?

Cheers,

Steve

Thu Feb 04, 2010 10:04 am   

On Feb 4, 12:22 am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:

You don't say how many SRAM chips. The first thing to consider in
evaluating SI (Signal Integrity) issues without a simulation is to
compare the length of the traces to the length of the edges of your
signals. The rule of thumb I have seen is that if the rising/falling
edges of your signals are six times longer than the length of the
trace (round trip) then you don't need to worry with reflections no
matter how many chips are in the path. All chips will see essentially
the same edges and there will be little ringing. Using an FPGA, you
can control the edge rates on the address bus. But on the data bus,
you can't control the edge rate from the SRAM chips. If it is too
fast (very likely with fast SRAM parts) the data bus will need to be
terminated. Terminating multipoint busses is nearly impossible and
even a simple two point bi-directional bus is not optimal but can be
done using series termination.

If you have enough I/O pins on your FPGA to use separate data busses
to the SRAMs, you can terminate each bus using a series resistor to
match impedance of the driver to the impedance of the trace. This
results in a reflection from the receiver, but the receiver sees the
proper transition (since it is the point of reflection) and the
reflection will not be reflected from the driver. If any other chips
are connected in the middle of this signal, they will see a half
voltage rise followed by a second rise to the full waveform voltage...
not what you want. But then, if you allow time for reflections to
settle in your timing analysis, you can ignore the SI issues on the
data and address busses and only be concerned about the timing signals
like the Write strobe. The address has to be stable by the leading
edge of the write strobe and the data has to be stable by the trailing
edge. On a read, you simply need to allow some extra time for bus
settling before the FPGA clocks the data in.



Likely, but you will need to consider a number of thing such as your
design rules in the layout.



Any voltage that will have switching currents on them should have a
power plane to optimally filter out the transients... in other words,
all of them. What family are you using that requires 2.5 volts as
well as 1.8??? I thought the recent stuff was all at 1.2 volts for
internal logic and the I/O voltage to match your needs. Are you
planning on using 2.5 volts for I/O or are you looking at an old
family? Or maybe I'm not remembering correctly???



They why use Eagle? I do my layouts in FreePCB. It doesn't support
back annotation actually, but I use forward annotation (updates). I
plan my pin swaps and add them to the schematic, reload the new net
list and then finish up the routes at the FPGA. It has been a while
since I have done this, so it may be trickier than I am remembering.
I find it very nice to be able to route with minimal vias. That also
helps to minimize the number of layers needed.



If this is your first board layout, leave yourself plenty of time and
do a lot of checking of your work as well as checking the tool.
There's many a slip twixt cup and lip. I found my first board layout
to be a real education...

Rick

Thu Feb 04, 2010 10:23 am   

On 04/02/2010 08:04, rickman wrote:

You have a lot more experience at this sort of thing than me, Rick, so
I'm a little wary of disagreeing with you. But I'm sure you'll tell me
if I get something wrong!

I don't see that you have to worry about any termination here. With
fast enough signal edges, you can get ringing - but that typically will
not matter because you don't sample the signals until the ringing has
subsided. When the FPGA is driving the signals, you have (as Rick says)
controllable rise and fall rates to avoid ringing. If you don't have
that, you will want to terminate critical signals like the read and
write strobes (or clock, for synchronous rams) to avoid triggering
multiple accesses. But other than that, just make sure the data and
address lines are stable before the strobes are sent. For reads, it's
possible that you will get ringing due to fast edges from the ram chips
(though that would require very over-spec'ed ram chips far away from the
FPGA), but you time your read sampling for after the lines have settled.

Ringing can cause a few problems - the overshoot/undershoot can go
outside the voltage range of the pins on the line, it can cause
interference for neighbouring signals, you can't read the signal while
it is ringing, and it can cause big trouble when connected to
edge-sensitive inputs. But most of these are not going to be a problem
in your case, I think.

If you need to access your rams in parallel, you will need multiple data
buses, and perhaps multiple address and control buses - that depends on
the application. But if you just want to access one at a time, I'd put
them all on the same bus. Routing between the chips will be easy, and
you have less lines from the FPGA to worry about. At the speeds you are
talking about, you should have no difficulties.


There is a big difference between "optimal" and "good enough". If the
design is fairly small and slow, with low currents, then wide traces to
the power pins and some capacitors is going to be perfectly sufficient -
there is no need for dedicated power planes for each supply.

Thu Feb 04, 2010 12:04 pm   

Thanks for the input so far, guys!

I will have two SRAM chips and one parallel EEPROM in one memory
space, and one additional RAM chip in a separate memory space so I
know for sure that that one gets its own dedicated address/control/
data lines.
I was just wondering if the signal integrity would be hurt by extra
loading in chaining up the ones that are on the same bus, but I had a
hunch that at these speeds it wouldn't be such a big problem.

And probably I will be using 10ns RAMs (I haven't looked at the rise/
fall times though) and keeping them physically as close as I can get
them to the FPGA.. maybe about a centimeter away, tops.
Looking at this old Digilent Spartan 3 board I have kicking around, I
don't see any termination between the FPGA and the ISSI SRAMs on
there, but each chip has its own address and data lines.. I dunno if
that's good enough to use as an example or not though.

As for the supply voltages, I'll be using a Virtex II, but this is the
first time I have started to think about implementing my own board and
thus needing to worry about power supplies, and I seemed to remember
some of my dev boards in the past having a couple or three different
regulators on board, but I didn't really think much about it. Looking
at the datasheet though, you're right, Rick, it appears that I just
need a single 1.5V supply for core voltage, and 3.3V for VCC_aux and
all of my I/O. I should have checked that and had the numbers right
before asking, sorry about that.
So if I need power planes for both of these voltages, do they each
need their own layer or can I arrange it carefully in one layer?

Thanks again,

Steve

Thu Feb 04, 2010 12:28 pm   

On 2/4/2010 8:23 AM, David Brown wrote:

Dear David, Steve,

Going "outside the voltage range of the pins on the line" can break the
device. IIRC there are Xilinx appnotes which go into this problem in
some detail; powering 3.3V with 3V was something I think they suggested!
(See XAPP653)
Also, the thing will probably fail any sort on electromagnetic
compliance test that you would need to do before you sell this. And you
are unlikely to be able to listen to 'The Archers' while this thing is
in the room.


To the OP, in the absence of micro-vias, I would recommend a 6 layer
board. Maybe like this:-

signal
signal
ground
ground
power/signal
signal

Keep all the layers as close together as your PCB manufacturer allows
and make up the board thickness with the core between the two ground
layers. Xilinx on the top. Route the powers, or use copper pours. Try to
make room for bypass caps on the back of the board from the FPGA. This
stack up will make it very difficult for a beginner to go wrong from an
SI point of view, as ground is always near. This is particularly true if
you have a nice spread of ground vias tying the two ground planes
together. That doesn't mean you shouldn't simulate it with Hyperlynx,
but I bet that won't happen! Always examine your ground plane pair at
the end of the routing process to make sure you haven't cut any big
slots in it with string of vias.

Finally, _real_ engineers use DRAMs! ;-)

HTH., Syms.

p.s. Did I make it clear that the ground is important?

Thu Feb 04, 2010 1:08 pm   

I suggest checking the data bus turn-off (->Z) time of the EEPROM. It migh
be rather long, meaning that an EEPROM read followed by an SRAM acces
causes data corruption.

If it is too long, either put an extra buffer with fast turn-off on th
board, or else use dedicated data signals and mux it in the FPGA.


---------------------------------------
Posted through http://www.FPGARelated.com

Thu Feb 04, 2010 1:24 pm   

TSMGrizzly <sbattazz_at_yahoo.co.jp> wrote:
....

Perhaps the net2ucf.pl Perl script I just uploaded to CADSOFT can help you
to generate LOC cobnstrains from an eagle netlist.

--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Thu Feb 04, 2010 1:57 pm   

On Feb 4, 7:28 pm, Symon <symon_bre...@hotmail.com> wrote:

Thanks all, for the good information! This will definitely help.

Uwe, I'll take a look at your script, that seems like it could be very
handy!

Symon, DRAM is out of the question in this design, gotta stick with
SRAM.. and it isn't really for sale, it's a custom one-off thing so I
don't think I have to worry about compliance tests.

I was hoping to keep the cost down a little by skimping on the layers
but I'm sure I can afford to go with six layers just fine.. six is
what I initially told the boss would probably be happening, I was just
wondering if I could get away with four.

Steve

Thu Feb 04, 2010 3:41 pm   

You can use 0402 resistors with 0.6mm round pads on 1mm centres.

This allows thm to be placed on the back of the BGA 'matching' the
BGA pads, and allows almost one cap per power & gnd pair.

Check with your assembly house that they're happy with this, mine does it
no problem (they built a couple of boards with 0.5mm pads before telling
me to make them bigger).



Nial

Thu Feb 04, 2010 4:38 pm   

Steve

I'll start by pointing you at Raggedstone1 http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
as an example of what can be done in 4 layers with a 456 pin BGA.

At speeds of 10-25Mhz I generally just about count that as DC and
don't really do anything other that what we do normally and that is
hand route. Handrouting, using your brain, gives much better results -
less vias, shorter tracks and so on and contributes a lot to a good
result. Frightening as might seem even our Merrick1 product with about
circa 18,000 routes is done that way.

If you can get away with just the outer 2 rows of ball you should be
able to use a "slack" technology of maybe 6mil/0.150mm track and gap
and that will save you money at manufacture.

On power split planes is a good technique if used very carefully but
using polygon fills on tracking layers will also help. On the
Raggedstone1 mentioned above there are something like 7 different
power rails under BGA and that was one the major difficulties with
that design so it's all possible. Later FPGA families do help by
reducing the need for so many rails.

On buses versus individual interfaces I would do buses at 25MHz. At
100MHz+ I would go the other way usually.

John Adair
Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board.

On 4 Feb, 05:22, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:

Fri Feb 05, 2010 2:15 am   

On 2/4/2010 1:41 PM, Nial Stewart wrote:

PCB fab's spec.

Cheers, Syms.

Fri Feb 05, 2010 4:32 am   

Awesome, thanks for the good information!

John,
I don't think I can get away with only the outer two rows of balls,
I'll probably need the two inside of that as well-- I was thinking of
breaking out the outer two on one signal layer and the inner two in
another, as suggested in the Xilinx app note I saw. It was a tight
squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
is the standard offering of the board house we're using.. it's
possible to ask for smaller, for an extra chunk of change.

Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.
I can imagine a scheme in which there are vias on each line going into
the first chip, connecting to wires on another layer to carry the
lines to the other chip where they are brought back to the component
side with more vias, but that's all I can come up with off the top of
my head

RCIngham, thanks for the heads-up on the EEPROM. I guess that the idea
is to have non-volatile data in it, and copy it to a section of SRAM
on power-up and then just read from SRAM during normal operation, but
I will still probably have to think about the time to 'Z' when
designing that data transfer part of the software.

cheers,

Steve

Fri Feb 05, 2010 5:43 am   

Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve

Fri Feb 05, 2010 8:26 am   

On Feb 4, 4:04 am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:

Signal integrity is not normally a direct result of the "loading" of
the parts. On most boards the effect of a pin on a bus is minimal.
If you split a run, like a fork in a river, it results in an impedance
mismatch and causes a reflection. The end of a trace is a high
impedance which also is an impedance mismatch and causes a
reflection. Three chips can be added to the board with trances as
short as maybe 2 inches. This is 4 inches round trip or about half a
ns. To avoid effects of reflection, the edge transition time should
be at least 3 ns. That is a *slow* edge. So expect noticeable
ringing. As has been said, on the data and address lines, you just
need to extend the setup times to wait it out to sample the bus when
it has quieted down. Figure three round trips or 1.5 ns extra. But
the write enable signal should be clean. The best way I know to do
that is to provide a separate write enable driver for each chip. Then
you can use series impedance matching in a point to point wiring so
that the receiver does not see any effects from reflection. Of course
this is assuming the write enable is the controlling pin when doing
writes. Some designs use the chip select to control the write
timing.



Are you going to try to use them as fast as possible? That can be
hard. If you can give each chip separate drivers for all signals, may
be able to keep the traces short enough to not see any reflection
effects. I may have muffed the math on this. That's the trouble with
rules of thumb. If you recall them incorrectly, it can be hard to
spot the error. Looking at this document,

http://techcircuits.net/docs/CriticalLength.pdf

It looks like I was overly pessimistic on the length. The rule of
thumb seems to be 1/3 instead of 1/6 so a 1 ns rise time won't cause
significant reflections, but I'm not sure about that. On page 7 they
use an analysis that I don't agree with. Basically, they are saying
this is the critical edge of timing and I don't think it is that clear
cut. I say use 1/6, but you can choose your own poison.



I would pick a newer family myself, but there is nothing wrong with a
Virtex II device. However, a newer family will be faster, lower power
and you will likely get better support. Of course you can overdo that
too. If you try to use the newest family, you may not get parts for
months and the tools may be a bit buggy... But Virtex 2??? Why not
Virtex 5 or even Virtex 4? The Spartan 3 chips are pretty good and
have been updated quite a bit although I don't recall which are the
latest and greatest. I know the S3 parts are FAPP not recommended for
new designs (at least by those of us here I expect) and the S3A parts
are pretty old at this point. Anyone, what are the newer S3x parts?

If you want to keep the power supply simple, Lattice has XP and
perhaps XP2 parts that use a single 3.3 volt supply and internally
drop it to the core voltage.



Yes, you can use one layer. I have a very tiny board <1" x 4.5" with
no less than four power planes on one layer, +12, +5, +3.3 and an
audio 3.3. There is another 1.8 volt plane in case I want to use an
FPGA with separate core voltage inputs, but that plane is on a
different layer shared with signal traces. I can't stress enough the
importance of power planes in keeping switching noise down. It is not
just a matter of adding a high frequency capacitor to the power rail,
it acts as a very low impedance transmission line connecting the
capacitors to the power pins of the chip. It is counter intuitive,
but it actually is not so important to keep the caps so close to the
chip if you are using good power planes. BTW, to maximize the
effectiveness of the power planes (read that as minimum impedance) you
want to have the power and ground plane as close together as
possible. 5 mils spacing should be practical and will go a long way
to doing a good job.

I found doing layout to be fun, but very intense! Most design
requires you to go back and forth between specs and data sheets and
the schematic capture package. Layout has some up front work getting
all the inputs and making the footprints, but then it just becomes a
really complex rubics cube with many possible solutions. Your job is
to find one that is pretty good without spending tons of time on it.

When I did my first layout, I contacted a couple of colleges and asked
them to do a design review with me. I was willing to pay them
consulting rates, but I was turned down. It turned out ok in the end,
but there were a couple of things that likely would have been caught
in a review. I am not very busy right now. If you would like and
when you are ready, I'd be willing to go through a design review with
you without charge. I'm pretty bored and would enjoy it.

Rick

Fri Feb 05, 2010 8:40 am   

On Feb 4, 5:28 am, Symon <symon_bre...@hotmail.com> wrote:

Everyone has their own way of doing things, but I would ask, why the
two ground planes? I would have a ground plane and a power plane in
the center with a minimum thickness between them. The spacing between
the ground/power plane and the signal plane is not so important. What
is important is the characteristic impedance. The lower the
impedance, the less it will radiate. Of course, with thin traces you
have to have the signal plane to power/ground plane very small to get
a low impedance. But if you have wide traces, you can open up the
plane spacing. Since the outer layers are on the outside of the
board, they won't be very close to inside power/ground planes. BTW,
you are aware that the power plane is just as effective as the ground
plane for determining the impedance.

Rick