Board layout for FPGA

Wed Feb 10, 2010 6:28 am   

On Feb 9, 2:10 pm, Symon <symon_bre...@hotmail.com> wrote:

Yes, I said I have not analyzed a complex PDS myself. But I have seen
it done by Lee Ritchey with very informative results. Those results
are the basis of what I have been saying here.


....snip...

Yes, I missed that. I would like to know where you got your info.
Now that you have me interested in this, I would like to understand
what you have done.



Lol!



Qualitative is not very useful. Everything has some effect on
everything. What is important is how *much* of an effect. There will
always be some ground and power noise. It is only a problem when it
becomes significant in comparison to the noise margins. Is that not
true? By only using one of each item in the design an unrealistic
representation of the circuit you are trying to propose. Clearly
there are a lot more than 1 board cap and via for each cap on the IC.
If I said the caps on the chip will have *no* effect, I did not mean
that. I intended to say that they would have no significant effect in
the region of interest.

Also, without understanding how you came up with the values used in
your simulation, I have no way to trust it.



Why do you say it is "on the die"? The value of Cin is largely from
the pin itself from what I have learned. Perhaps I am wrong, but it
makes sense to me that the pin has more capacitance than the
transistor on the die, but I may not be right on that. How can you
tell this capacitance is of the transistor and not the pin?



I'm not at all clear on that. The capacitance of the trace is very
significant. If you said the trace and other IC pins shouldn't be
modeled as a lumped capacitance, I would agree that might be
significant, but to say it is not important at all is not obvious
without something to support that.



Ok, then I agree that there will be some effect from the on chip
caps. But I don't agree that they are useful in reducing ground
bounce from I/O switching.



Yes, I have used this simulator before. But a simulation is only as
useful as the circuit being simulated. If you try to simulate a
complex PDS without verifying it with measurement, you have no idea if
your simulation is correct. I believe the "mailing list" is actually
a Yahoo group which is a *great* place to get excellent support. I
forget the name of the LT person, but he answers every question he can
with patience and never chids no matter how many times that same
question has been answered. It would appear that responding to that
group is his full time job at LT!

I will say that the Ritchey course is full of examples of designers
who follow rules of thumb without knowing why or that use an incorrect
analysis without ever verifying it with the real world. There are
even examples of companies that went out of business because of
designers who did not completely understand why their circuits did not
work correctly.

Maybe I will perform this simulation the way I think it should be
done. Then we will see if closely coupled power planes are pointless
or not...

Rick

Thu Feb 11, 2010 11:05 am   

I'm about to start the layout on a board which I think needs
a 10 layer stack.

After the religious wars betwen rickman and Symon on decoupling I'm
unsure on the best stack but am veering towards...

1 signal - Top
2 GND plane
3 signal
4 signal
5 PWR plane
6 GND plane
7 signal
8 signal
9 PWR & GND plane
10 signal - Bottom


There will almost definitely be power pours on layer 9, the BGA
will be on the top layer.



Comments?

Thu Feb 11, 2010 4:16 pm   

On Feb 11, 5:05 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:

If you're planning a solid plane for the "PWR plane" on
layer 5, I'd probably swap that one with layer 9 so you'd
have a solid plane near the bottom. Otherwise you need
to be careful routing high speed signals across the plane
splits on layers 8 and 10.

Regards,
Gabor

Thu Feb 11, 2010 9:14 pm   

My "religion" does not tell you how to make a stackup without more
information.

Do you need to set specific impedance on any traces? If so, what
values, number of traces and approximate length.

Do you expect any EMI issues? What is your fastest edge rate?

The way you have your stack set up seems to be optimized for
controlling trace impedance by having a gnd/pwr layer immediately
adjacent to each signal layer. The stackup below will give you a
stackup optimized for power distribution and still allow for impedance
control if you can adjust your trace width to suit. I assume you have
read the arguments pro and con the significance of inter plane
capacitance. With the stackup below, you can still get good impedance
control on the outer layers with slightly wider traces. But you won't
be routing too many signals on the outer layers if your board is at
all dense, the components eat up al the routing space. It will be
important on *all* layers to minimize routing of signals one above the
other on adjacent layers to prevent coupling and crosstalk. The easy
remedy is to route orthogonally on adjacent layers. It also provides
a good means of getting signals around the board with minimal vias
which is important.

1 signal - Top
2 signal
3 GND plane -- >= 5 mil to PWR plane 4
4 PWR plane
5 signal
6 signal
7 GND plane -- >= 5 mil to PWR plane 8
8 PWR plane
9 signal
10 signal - Bottom

With ten layers the average thickness (using 1/2 oz copper) is about 6
mil. You will likely make it a little thicker between layers 4, 5, 6
and 7 since that is stripline rather than microstrip. You will want
to use very thin layers between 3 & 4 and 7 & 8 to maximize PDS
capacitance.

If you want to go for maximum signal isolation from crosstalk, I would
isolate all signal layers with power and ground.

1 signal - Top
2 GND plane
3 signal
4 PWR plane
5 signal
6 signal
7 GND plane
8 signal
9 PWR plane
10 signal - Bottom

Well, I guess 5 and 6 are still adjacent, but you can't have
everything... This arrangement does lend itself to ground pours on
all signal layers other than 5 and 6. If you use ground pours on
layers 5 and 6 it will much with the impedance control because of the
routing on the adjacent signal layer.

This is just a seat-of-the-pants analysis. If you need impedance
control on all layers, you would need to analyze each signal layer in
terms of impedance vs. trace width. You may find that your approach
is better for your specific needs.

Can you explain the rational behind your stackup? I don't want to
argue about it, I just want to learn what you are thinking.


On Feb 11, 5:05 am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:

I wouldn't bother mixing ground and power on one layer. Even with a
couple of signal layers between, you will get significant capacitance
between the power and ground. Since the power layers act as ground
for high frequency signals you don't need the ground on layer 9 unless
it is for connectivity. Are you expecting gnd layers 6 and 2 to be
chopped up? With two power layers they will be much less chopped up
if you have more than two power voltages.

Rick

Tue Feb 16, 2010 6:56 pm   

On Feb 9, 3:15 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

I think I have figured out why you *don't* need to consider a radial
transmission line in models of the PDS. The transmission line model
is only effective if the length of the line is longer than about 1/6th
of the rising edge of the signal. For a 0.5 ns rise time pulse the
rising edge is about 3 inches in length on the PWB. So if you keep
your caps within a half inch of the power pins of the chip, the
transmission line effects are spread over the entire path (or averaged
if you will). In other words, for adequately short paths, the
electrical path between the power pins and decoupling caps appears as
a lumped capacitance and does not need to be analyzed as a
transmission line.

Does that sound right?

Rick

Tue Feb 16, 2010 10:17 pm   

rickman <gnuarm_at_gmail.com> wrote:
(snip, I wrote)


It does seem that the previously mentioned papers analyze them
in ways that I wouldn't think would matter. One even considers
the reflection of other vias.

But, there are a few things that I think should be considered.
The inductance of the via, and the input impedance of the radial
transmission line are proportional to 1/r. Big vias are better.
A group of vias close enough together, though, should act like
a large via. (The fields couple such that it isn't the same
as parallel inductors.)

It would seem that one should also be careful not to put the FPGA
right in the center of a large ground plane, such the the edge
reflections come back in phase. That would be especially bad for
a large circular ground plane. If the decoupling capacitors were
regularly spaced, that could also cause in-phase reflections.


It doesn't seem so far off. It still seems that radial transmission
line theory isn't taught much at all.

-- glen

Wed Feb 17, 2010 2:57 am   

On Feb 16, 3:17 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

I am confused. You say that my analysis is not far off and the whole
(hole) point of my analysis is to show that the radial transmission
line effect is not important. Then you say you still think the radial
transmission line effect *is* important.

I am pretty sure that the effects of the decoupling caps swamps out
the effect of the reflections. This is not very scientific and so may
be totally wrong, but it would seem to me that the caps will "mute"
the voltage transitions on the plane as the wave moves by. If it were
a linear transmission line, the cap would "smear" out the edge of the
wave front. In the PCB power plane the same thing happens, but it is
likely strongest at the cap and is a weaker effect further away from
the cap. In the case of a transient, smearing it out reduces the
amplitude which is exactly what it is supposed to do. So I expect the
wave front never reaches a board edge to cause a significant
reflection. I will say that when the impedance of a PDS is measured
the very high frequencies often have a sawtooth shape which is likely
due to standing waves on the board. So there must be some of the
transient that is reflected.

But if you can verify your analysis method by measuring the impedance
of the PDS to be below your requirements at all frequencies, what does
it matter if the power planes form a "radial transmission line"? You
only need to do enough analysis to get a "good enough" result. I
would think that if this were an important effect, that would have
been discovered by now.

Rick

Wed Feb 17, 2010 3:31 am   

rickman <gnuarm_at_gmail.com> wrote:
(snip, I wrote)


If it works right, the capacitor should be an AC short between the
planes. If, for example, you had a ring of capacitors around
a constant radius from a via, then the reflection off those should
come back in phase. That is pretty much the same as a microwave
cavity resonator.


A capacitor across a linear transmission line should make a nice
reflection. A capacitor and series resistor should absorb some
of the AC signal, but ignore the DC voltage. Though that assumes
ideal capacitors.


In a real board with lots of ICs, vias, and bypass capacitors,
you would hope that the reflections are rarely in phase. If parts
are placed too regularly on the board, it would seem possible for
some strong resonance to form.


I think it only really matters for a very short distance. For that
distance, though, it should be computed as a radial transmission line.


There have been plenty of cases where effects when unnoticed for
way too long. If, for example, a board resonance turned out to
be the same as an on-board frequency it could easily be very
significant. Then an unrelated change would move the resonance,
and the problem would go away without ever being found.

-- glen

Wed Feb 17, 2010 8:04 am   

On Feb 16, 8:32 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

You are still talking about the reflections from the caps and I have
already shown that the caps don't cause reflections as long as they
are very close to the vias connecting the power pins. The wavelength
of the transients are too long so that only a portion of the edge is
ever distributed across the transmission line between the via and the
cap. The result is that the reflection is insignificant and the cap
acts to suppress the wavefront and not let it pass beyond the region
around the cap.



But not if the transition time of the edge is slow compared to the
transit time to the cap. The reflection would be the opposite phase,
but much, much smaller in amplitude than the full transient.
Meanwhile the amount of the transient passing the cap would also be
very small because most of the energy is reflected.



I don't mean to repeat myself endlessly, but I don't think you will
see much of the reflections. The wave front does not pass the area
around the cap since it is absorbed by the cap. The reflection from
the cap is opposite in phase as the original transient and is only
displaced a fraction of the width of the transient so it nearly
cancels out in all directions. The degree to which it cancels out
depends on the time offset of the reflection which is determined by
the spacing between the cap and the power via and the strength of the
reflection which in turn depends on the impedance of the cap at that
frequency. The reflection is a good thing, not a bad thing. That is
what reduces the transient!



I t would seem to me to make more of a difference over a larger
distance where the impedance seen varies much more. If you think of
it as an impedance that reduces with distance from the power via, it
would create a continuous reflection back to the via, in effect
reducing the amplitude of the transient. Imagine many, small
reflections with only a very slight difference in phase summing up.
In effect, it would be a lot like a lumped capacitance right at the
via I think.



If that resonance were causing a problem, I would expect that it would
be noticed and recognized at some point. Any given board might have
some change made which will cause the problem to "go away", but I
can't believe at this point in time no one would have ever seen this
and recognized it for what it was. Why make up problems if they don't
exist?

Rick