Board layout for FPGA

What resonance?

Symon<symon_brewer_at_hotmail.com> wrote:

(snip on bypass capacitors)

What resonance?

The limit to the useful frequency range of a capacitor is
when it reaches resonance with the series (lead, package, etc.)
inductance. Graph impedance vs. frequency, when the reactive
component crosses zero that it resonance.

-- glen

In comp.arch.fpga rickman <gnu...@gmail.com> wrote:
(snip)

My bad here.  I am the one saying that the planes will capacitively
couple and allow the return current to cross slots in one plane by
jumping to the other.  I got your post mixed up with Symon's post
where he recommends multiple ground planes stitched together with vias
rather than capacitively coupled power/ground planes.

Well, you want it to stay low impedance all the way down to DC.

(snip, I wrote)
I completely agree. ?Well, actually computers are probably about
fast enough to do the whole calculation for at least one board trace
using the actual geometry. ?With linearity you can compute each one
and add them together. ?
Lee has done that. ?One test he made
that really impressed me was to show that a decoupling cap does not
need to be close to a pin to work well. ?If the power and ground plane
are closely spaced, the impedance is very low. ?If you understand
transmission lines, you will know that the current into (or out of) a
driver into the transmission line is constant until the signal reaches
the other end and depending on what load it finds, either continues
until the reflection returns to the driver (as in a series terminated
line with high impedance load) or keeps flowing as when it reaches the
decoupling cap. ?
Well, it has the impedance of the transmission line itself.
That depends on the inductance and capacitance of the conductors
making up the transmission line. ?You can consider a linear
transmission line as a sequence of series inductors and parallel
capacitors of constant value per unit length. ?Consider the
impedance of a finite length open ended transmission line as
a function of frequency. ?For some frequencies the impedance will
be very low, for others it will be very high. ?This property
is used for impedance matching and filtering in RF circuits.
I am aware of what a transmission line is.  That is my point.  The
transmission line of closely spaced planes is a very low impedance
which supplies current for the full time it takes the impulse to reach
the cap.  So the spacing of the caps is not at all critical contrary
to what many will tell you.

I believe, though, that radial transmission lines aren't
discussed much in classes.  I hadn't thought of them much until
I was replying to your post.  A google search for them brought
up the paper that I tried to reference.  I did the search on a
different computer and copied the link by hand.  I will try again.

Now, consider the case of a signal going into or out of a supply
plane. ?Now instead of the constant inductance and capacitance
per unit length you have concentric rings. ?The inductance decreases
and the capacitance increase with radial distance. ?In transmission
line terms, it is a line with the impedance decreasing with R.
Impedance decreases pretty fast, too. ?
A quick web search finds a paper that looks interesting on just
this problem. ?
http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf
The paper has much more detail than even I know, and includes
comparisons of calculations and actual boards.
What paper?  I get a 404 error, page not found.  Still, I don't see
the problem you seem to be describing.  So the impedance drops with
increasing distance, low impedance in the power supply is a good
thing, no?  Why would it dropping be a bad thing?

OK, try again.

   http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf

he seems to even include the reflections of other vias, which
seems more than is needed to me, but...

It looks like the other papers on on slot antenna design,
so he is considering PC board design in slot antenna terms.

Lee actually has impedance vs. frequency measurements of power/ground
planes and it is pretty interesting.  They don't do much below 100 MHz
or so, but beyond that the impedance is an up/down trace (all
adequately low) until it finally starts to climb above several GHz.
IIRC he explained the the sawtooth as having to do with the board
dimensions.  I guess it has something to do with standing waves, but
it was some four years ago and I don't recall for sure.

With some bad luck you might get a resonance (standing wave)
where the impedance didn't stay low.

I do remember that he showed some interesting interactions between the
plane capacitance and the inductance of the small sized and valued
decoupling caps.  They have a resonance around 100-200 MHz I think,
which drives the impedance way up at that value.  His solution was to
add other value caps which effectively move that resonance and also
damp it out to where it is acceptable.  I think he showed a board
where he used a total of three different values of ceramic caps, but
only a small number of each, to get a very quiet board with a very
constant power delivery system impedance.  When I took the course, I
understood how to figure it all out, but I have not had a design with
difficult power decoupling needs, so I have forgotten some of it.
Good thing I still have the book... somewhere...

In the old days, it might be that the tolerance kept the resonances
from being too close.  The uniformity is so good now that they
will all have resonance too close together.

So the physics of each board is different???  The board Lee
constructed was a test board.  I don't recall what he used for a
source of the transient, but he had spots for capacitors at a minimum
of three distances connected to the power/ground planes with optimally
short runs to the vias.  He populated the caps one at a time and
measured the effectiveness finding that it dropped off barely at all
at an inch, IIRC and only moderately at a couple or three inches.  The
point is that it is not really needed to put the cap right on top of
the power pin.  A good power/ground plane pair is much more
important.

(snip)

My point is that this is all theory.  Unless you take some
measurements to verify what you are saying, you can't say it is an
accurate description of a real board and chip.  Also consider that one
via is not a power supply.  Vias are used in parallel giving an
effectively low impedance.

Hopefully the link is right now.  He does both theory and measurement.

On 2/6/2010 6:15 PM, rickman wrote:

will increase with frequency.

My point is that this is all theory.  Unless you take some
measurements to verify what you are saying, you can't say it is an
accurate description of a real board and chip.  Also consider that one
via is not a power supply.  Vias are used in parallel giving an
effectively low impedance.

Rick

Rick,
Do you measure every resistor you put on a board. Ohm's law is a theory,
after all.
Syms xx

On 2/6/2010 5:38 PM, rickman wrote:

I keep asking you if you have done any real analysis or measurements
of what you are stating?

 

Well, this was the first time you asked IIRC, but thank you for doing
so. The answer is "For sure". I've used Hyperlynx and Spice on my
boards. I guess you have also, or else you would not be able to post
your opinions without worrying you might giving someone a bum steer.

I am no guru,

Really?

 

but I was *very* impressed by
what Lee Ritchey said just because he has full support for just about
everything he stated in his course (except maybe that the food was
good at the Chinese restaurant).

Rick

You seem to be _very_ impressed. Almost as impressed as Steve Wier.

http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4

On 2/7/2010 1:03 AM, glen herrmannsfeldt wrote:

Symon<symon_bre...@hotmail.com>  wrote:

(snip on bypass capacitors)

What resonance?

The limit to the useful frequency range of a capacitor is
when it reaches resonance with the series (lead, package, etc.)
inductance.    Graph impedance vs. frequency, when the reactive
component crosses zero that it resonance.

-- glen

Hi Glen,
Are you sure? Even beyond that frequency the cap is still doing
something, isn't it?
Syms.

? ?http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf

I still can't read it. 404 not found error again.

I'll have to wait until another day. BTW, does he actually relate
this to power supply decoupling or is this just a transmission line
analysis?

Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.


Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve

On 05/02/2010 03:43, TSMGrizzly wrote:





Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.

Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve

Are you thinking that, for example, pin D0 on one ram device is on the
same bus line as pin D3 on the next ram device?  That's certainly
possible - for static ram, there is no difference between the data lines
or most of the address lines (if the ram supports bursting of some sort,
then some address lines are specific).

However, the easiest way to connect multiple identical ram devices on a
pcb is to simply place them close together and carefully aligned - then
you can "bus route" between them with a neat pattern of routes straight
across.  Only the chip select line is handled separately.  Mixing the
bus numbering is not going to be of any benefit here, and it will make
your schematics somewhat more confusing.

On Feb 6, 7:37 pm, Symon<symon_bre...@hotmail.com> wrote:
On 2/6/2010 5:38 PM, rickman wrote:

I keep asking you if you have done any real analysis or measurements
of what you are stating?



Well, this was the first time you asked IIRC, but thank you for doing
so. The answer is "For sure". I've used Hyperlynx and Spice on my
boards. I guess you have also, or else you would not be able to post
your opinions without worrying you might giving someone a bum steer.

So are you going to share the results of these simulations on the vias
you are talking about?


Sure Rick, let's go through it together with some cheap tools (free!)

3) Power plane bypassing systems can give rise to nasty unexpected
resonances unless they are designed very carefully as shown in
experiment 5. Using crappy Q bypass capacitors instead precludes this
from ever being a problem.

I'd appreciate your critique.

Thanks, Syms.

big snip


3) Power plane bypassing systems can give rise to nasty unexpected
resonances unless they are designed very carefully as shown in
experiment 5. Using crappy Q bypass capacitors instead precludes this
from ever being a problem.

I'd appreciate your critique.

Thanks, Syms.


snip

So, are X7R 'crappy' enough Q, or would Y5U be worse/better?


---------------------------------------
Posted through http://www.FPGARelated.com

On 2/8/2010 5:14 AM, rickman wrote:

On Feb 6, 7:37 pm, Symon<symon_bre...@hotmail.com> wrote:
On 2/6/2010 5:38 PM, rickman wrote:

I keep asking you if you have done any real analysis or measurements
of what you are stating?

Well, this was the first time you asked IIRC, but thank you for doing
so. The answer is "For sure". I've used Hyperlynx and Spice on my
boards. I guess you have also, or else you would not be able to post
your opinions without worrying you might giving someone a bum steer.

So are you going to share the results of these simulations on the vias
you are talking about?

Sure Rick, let's go through it together with some cheap tools (free!)
from t'internet. OK, you can get a nice copy of Spice from here. maybe
you already have it.

http://www.linear.com/designtools/software/

At the bottom of this post you will find a model of a PCB with a power
plane bypass. I've used lumped components to model it. If you
cut'n'paste the text into an editor and save it as 'planes.asc' or
somesuch, you should be able to load it into the simulator you downloaded..

So, if you look at the model, here's what each bit does.

V1 DC power supply.
L3 Big inductor to represent the PDS supply impedance.
C2, R2, L4 model a 0402 1uF bypass capacitor. L4 includes the vias.
C4 Models the power plane bypass. No parasitics on this baby!
L1 Models the power via and ball from the plane to the FPGA die.
C3, R3, L5 model the bypass capacitor on the FPGA BGA package.
R1, C1, V2 model a IOB switching with 500ps rise time. Rout=20,Cpin=10p
L2 Models the ground via from the PCB plane to the FPGA die.

BTW, you can find models of bypass capacitors here:-http://www.murata.com/products/design_support/mcsil/index.html

Signals are:-

PCB_PWR is the power on the PCB
FPGA_PWR is the power on the BGA package.
FPGA_GND is the ground on the BGA package.
Vout is used to show when the switching happens.

(1) If you press the little 'running man' button, a simulation window
will appear. You can now click on nets in the schematic. I clicked on
FPGA_PWR, FPGA_GND, Vout and PCB_PWR. I also clicked on Windows -> tile
vertically to give a nicer picture. Whatever, let's call this experiment 1.

OK, we see the power on the BGA is quite well behaved as expected. 60mv
of overshoot and ground bounce.

(2) So, what happens if we remove the bypass made from the power plane
being next to the ground plane, and instead use a ground plane near the
surface? If you make the schematic the active window by clicking in it,
then click the scissors symbol, then click on C4, that's got rid of the
power bypassing. If we right click on L2 and change it to 0.5n, (N.B.
don't forget the 'n'!) that's the same as moving the ground plane near
to the surface, as the via inductance is reduced by this much. Call this
experiment 2.

Here we see a little difference. The power overshoot is now a bit
bigger, maybe 110mV. The ground bounce is less, about 30mV.

(3) If we add another bypass capacitor, using the copy feature (next to
the scissors!) to copy L4, R2 and C2, we can do experiment 3.

Here we see smaller overshoot, maybe 100mV, showing that if a few bypass
capacitors are added we would get back the performance of a 'plane built
capacitor'.

(4) Let's go back to the original design. If you press F9 enough times
you'll undo any changes. Try deleting the 'on BGA' bypass capacitor C3.
experiment 4.

You will now see much bigger overshoots and ground bounce. That's why
the FPGA manufacturers put bypassing on the BGA.

(5) OK, back to the original design again with F9. Let's try this. Let's
say we only have a small board, a few square inches, and the plane
capacitance is only 200pF. Right click on C4 and change it to 200p.
Experiment 5.

Here we see the potential danger of using a power plane derived
bypassing system. The high-Q power plane is resonanting with L1, the via
and ball inductance to start an oscillation. With ordinary bypass
capacitors only, this doesn't happen as the caps have far less Q. If you
remove the 'on-bga' bypassing, C3, you'll see this effect get even worse.

I hope this crude model has given you some insight into why I choose to
eschew the power plane bypassing idea in the middle of the board, and
use ground planes near the surface instead.

1) From experiment 2 we can have less ground bounce by using a ground
plane very close to the FPGA. The ground is connected to all the FPGA
supplies, not just the Vcco we are simulating here, so is most
important. Any ground bounce affects the whole device, core, DCMs, PLLs,
everything. Any rises in Vcco overshoot from losing the power plane can
be mitigated with more bypass caps as shown in experiment 3.

2) The manufacturers put bypassing on the device for a reason, as we see
from experiment 4, and this is highly effective.

3) Power plane bypassing systems can give rise to nasty unexpected
resonances unless they are designed very carefully as shown in
experiment 5. Using crappy Q bypass capacitors instead precludes this
from ever being a problem.

I'd appreciate your critique.

Thanks, Syms.

Model planes.asc :-

Version 4
SHEET 1 880 680
WIRE -144 -224 -192 -224
WIRE -16 -224 -64 -224
WIRE 128 -224 -16 -224
WIRE 272 -224 128 -224
WIRE 336 -224 272 -224
WIRE 336 -192 336 -224
WIRE -16 -128 -16 -224
WIRE 336 -96 336 -112
WIRE 528 -96 336 -96
WIRE 560 -96 528 -96
WIRE 336 -80 336 -96
WIRE 336 -80 224 -80
WIRE 336 -64 336 -80
WIRE 224 -48 224 -80
WIRE -16 16 -16 -48
WIRE 128 48 128 -224
WIRE 224 48 224 32
WIRE 336 48 336 16
WIRE -192 80 -192 -224
WIRE 336 128 336 112
WIRE 528 128 336 128
WIRE 560 128 528 128
WIRE 224 144 224 128
WIRE 336 144 336 128
WIRE -16 176 -16 96
WIRE 224 256 224 208
WIRE 336 256 336 224
WIRE 336 256 224 256
WIRE 336 288 336 256
WIRE 528 288 336 288
WIRE 560 288 528 288
WIRE 336 320 336 288
WIRE -192 432 -192 160
WIRE -16 432 -16 240
WIRE -16 432 -192 432
WIRE 128 432 128 112
WIRE 128 432 -16 432
WIRE 256 432 128 432
WIRE 336 432 336 400
WIRE 336 432 256 432
WIRE 256 464 256 432
FLAG 256 464 0
FLAG 528 -96 FPGA_PWR
FLAG 528 288 FPGA_GND
FLAG 528 128 Vout
FLAG 272 -224 PCB_PWR
SYMBOL ind 320 -208 R0
SYMATTR InstName L1
SYMATTR Value 1n
SYMBOL ind 320 304 R0
SYMATTR InstName L2
SYMATTR Value 1n
SYMBOL voltage -192 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL voltage 336 128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 3.3 0 0.5n 0.5n 9.5n 20n)
SYMBOL cap 320 48 R0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL res 320 -80 R0
SYMATTR InstName R1
SYMATTR Value 20
SYMBOL ind -48 -240 R90
WINDOW 0 5 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName L3
SYMATTR Value 10µ
SYMBOL cap -32 176 R0
SYMATTR InstName C2
SYMATTR Value 1µ
SYMBOL res -32 0 R0
SYMATTR InstName R2
SYMATTR Value 0.25
SYMBOL cap 208 144 R0
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL ind 208 -64 R0
SYMATTR InstName L5
SYMATTR Value 0.7n
SYMBOL cap 112 48 R0
SYMATTR InstName C4
SYMATTR Value 1n
SYMBOL ind -32 -144 R0
SYMATTR InstName L4
SYMATTR Value 0.7n
SYMBOL res 208 32 R0
SYMATTR InstName R3
SYMATTR Value 0.25
TEXT -312 -72 Left 0 !.tran 50n

This is becoming a very informative discussion. I have not tried to
analyze a complex power distribution system (PDS). Most of the
devices I build have modest PDS needs.

You didn't go into enough detail on how you picked the values you
used. I do not typically use 1 uF caps as decoupling caps. I use
either 100 nF or 10 nF or a combination of the two. I see you used a
10 nF cap on the IC. You list the Murata tool as the source of the
capacitor parameters, but the values you use for ESR seem very high.
With that tool a GRM188R71H103KA01 in the 0603 package gives a series
inductance of 0.58 nH and a series resistance of 0.094 at 100 MHz.
This frequency is above the self resonant frequency of about 65 MHz,
but the impedance is still only 0.23 ohms, same as at about 42 MHz.

You also did not include any of the parasitic effects of how the
capacitors connect to their substrate. In the case of the board
mounted caps, they will have vias connecting them to the power
planes. In the case of the caps inside the package, they will also
have mounting parasitic effects, even if there are no vias.

I guess you missed "L4 includes the vias"? I modeled the vias by lumping

But none of that really matters. Your circuit is a very poor
representation of the real world.

That is why it is so important to
verify results with real world measurements. Your circuit has several
problems. The first is that you only apply a single decoupling
capacitor to the board! I may be an advocate of using fewer
decoupling capacitors, but I think one is pushing the envelope a bit
much. If you gave a reference to finding a value for the inductance
of the connection between the power plane and the chip die, it must
have been in an earlier post.

But most importantly, I am very sure that your model for how the
transients are generated is wrong. You show the current path as being
from the FPGA power plane directly through the output series
resistance and back to the FPGA ground. I am pretty sure that none of
the traces on the board (the source of the capacitive load on the
output) directly connect to the FPGA ground.

You need to put that
connection to the board ground, and even then through another package
lead. The model of using a signal generator to provide current surges
may not be so good as well. This results in currents being drawn
between the two FPGA planes. Perhaps I am reading incorrectly that
the Vout is an I/O pin and you are only trying to model internal
switching transients. The real issue that causes ground bounce (the
thing you seem to be most concerned about) is the current required to
charge and discharge the board trace and component pin on the other
end of that trace.

This current will by necessity pass through the
two inductors (L1, L2) and will create a lot of bounce that is not
mitigated by the on chip capacitor(s).

Even if you are looking at the internal switching noise of the IC, you
need to model the *entire* PDS, not just one pin or one capacitor at a
time. You also need to pick appropriate values for the various
components and include all parasitic effects. If you can't do all of
that, or even if you can, a simulation doesn't mean squat if it isn't
complete.

The only way to know if it is complete for something as
complex as this is to take measurements of a real design.

Rick

Sure Rick, let's go through it together with some cheap tools (free!)
from t'internet. OK, you can get a nice copy of Spice from here. maybe
you already have it.

http://www.linear.com/designtools/software/

At the bottom of this post you will find a model of a PCB with a power
plane bypass. I've used lumped components to model it. If you
cut'n'paste the text into an editor and save it as 'planes.asc' or
somesuch, you should be able to load it into the simulator you downloaded.