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glen herrmannsfeldt
Guest
Fri Feb 05, 2010 11:53 pm
rickman <gnuarm_at_gmail.com> wrote:
Quote:
On Feb 5, 8:45 am, Symon <symon_bre...@hotmail.com> wrote:
(really big snip)
Quote:
with a thick centre core and routed powers. This way the internal signal
layers are shielded. I tend to agree. The ssggss stack I suggested
because I almost always use laser drilled micro-vias on my boards, so I
need two signal layers on the outside. Also, my enclosures do the EMC
shielding. With standard vias, sgssgs is probably better.
(snip)
Quote:
As to the return current having to "jump" between layers being a
problem, if you use the ssgpss stackup and have the power and ground
very close rather than widely spaced, the capacitive coupling allows
the signal to switch between them without issue. In fact, when
splitting a plane for multiple power sections, the return current will
switch from one power plane, to the ground plane and back to the next
power plane as if they were all one plane. This is because of the
capacitive coupling between layers. Of course this only works for the
highest frequency components of the signals, but that's all we really
care about, no?
-------+ +-------> Return Current
=======| |======== Power Planes
| |
+--+
=================== Ground Plane
Yes. Actually, I believe that for the really highest frequency
components, that they are supplied by the plane itself. (Especially
as signals won't be switching at exactly the same time.)
The slightly lower ones, but only slightly, will take the path
you mention. Frequencies with wavelength shorter than the long
path around won't be able to take that path. The lower frequencies
are still there, though, but at low enough levels that ordinary
bypass capacitors and interplane capacitance will take care of them.
-- glen
Symon
Guest
Sat Feb 06, 2010 2:42 am
On 2/5/2010 9:53 PM, glen herrmannsfeldt wrote:
Quote:
Yes. Actually, I believe that for the really highest frequency
components, that they are supplied by the plane itself. (Especially
as signals won't be switching at exactly the same time.)
Hi Glen,
If these highest frequencies are supplied by the planes, why do Xilinx
and Altera put capacitors on the BGA substrate? That must cost money.
Are they wrong?
Thanks, Symon.
glen herrmannsfeldt
Guest
Sat Feb 06, 2010 3:33 am
Symon <symon_brewer_at_hotmail.com> wrote:
Quote:
On 2/5/2010 9:53 PM, glen herrmannsfeldt wrote:
Yes. Actually, I believe that for the really highest frequency
components, that they are supplied by the plane itself. (Especially
as signals won't be switching at exactly the same time.)
If these highest frequencies are supplied by the planes, why do Xilinx
and Altera put capacitors on the BGA substrate? That must cost money.
Are they wrong?
OK, not quite the highest frequencies, but almost.
The highest that get through the inductance of the package and
past the internal capacitors.
I think it isn't so hard to calculate the impedance of an
infinite plane with a hole (via) as a function of frequency.
That should partly answer the question.
-- glen
whygee
Guest
Sat Feb 06, 2010 9:42 am
Hi Rick !
rickman wrote:
Quote:
Lee Ritchey showed me (that only a fraction of the number
of caps normally used are really needed) but I still try to use one
per power pin! Call it superstition or just lack of confidence in
myself. But no one's design failed because he used too many caps on
the power plane.
Excellent point, I feel concerned by this remark :-)
Quote:
Rick
yg
--
http://ygdes.com /
http://yasep.org
rickman
Guest
Sat Feb 06, 2010 9:50 am
On Feb 5, 4:38 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Quote:
(comp.dsp added, as there are people there who consider these problems.)
rickman <gnu...@gmail.com> wrote:
On Feb 5, 6:42 am, Symon <symon_bre...@hotmail.com> wrote:
(snip)
So, I recommend multiple ground planes close to all your signals. A
thick core in the centre of the board to make up the correct thickness.
Then you can simply forget about any slot issues. Like you say, this
lets you keep the traces thin and with a lower characteristic impedance,
which is normally what you want when routing BGA FPGAs. The two ground
planes should be well bonded with vias, so there isn't a problem when a
signal goes through a via and passes from being referred to one ground
plane to the other.
Below, you talk about the connecting of the power and ground plane by
spacing to be of little value and yet propose that vias are adequate
to couple multiple ground planes. I find that interesting. For a
signal passing between layers the return current would have a long
path to reach a via and back.
I believe, for the most part, it doesn't do that. The capacitance
of even a single plane is high enough at the higher frequencies
that for the most part the return current doesn't have to take
the long way around.
What do you base this on? And what do you mean by the "capacitance of
even a single plane"??? What is the sound of one hand clapping?
Isn't capacitance measured between two conductors? Above you said,
"The two ground planes should be well bonded with vias, so there isn't
a problem when a signal goes through a via and passes from being
referred to one ground plane to the other." How is bonding the planes
with vias useful if the current has to go all the way to a via and
back in order to follow the trace???
Quote:
I reject the notion of placing a power plane and a ground plane close
together in the middle of the board to get the benefit of the
inter-plane capacitance for bypassing reasons. Don't get me wrong, it
won't hurt, but IMO the amount of capacitance gained is tiny, and even
though it is a very high Q capacitor, getting the power to the die is
stymied by the inductance of the vias and BGA balls that are part of the
PDS.
I think I agree with this. The way to actually see this is to
calculate the radial propagation of the signal into the plane
from the via. The impedance (both inductance and capacitance)
will change with radial distance and frequency.
That is why Lee Ritchey's course was such an eye opener for me. There
are any number of ways you can "calculate" and theorize what happens
in power planes. But unless you verify it by testing in hardware, you
are just whistling in the dark. Lee has done that. One test he made
that really impressed me was to show that a decoupling cap does not
need to be close to a pin to work well. If the power and ground plane
are closely spaced, the impedance is very low. If you understand
transmission lines, you will know that the current into (or out of) a
driver into the transmission line is constant until the signal reaches
the other end and depending on what load it finds, either continues
until the reflection returns to the driver (as in a series terminated
line with high impedance load) or keeps flowing as when it reaches the
decoupling cap. So if the cap is further away, the transmission line
supplies the current for decoupling until the wave front reaches the
cap. The point is that the planes have to be closely coupled for
there to be a high enough capacitance (also known as a low enough
impedance) to provide the current until the pulse reaches the cap.
Lee actually built a board and has measurement data to show this. So
analyze away if you want, but how can you dispute measurements?
Quote:
If your power plane is in the middle of the board, the signal path
of these vias are longer. You don't care about the supply stiffness on
your plane, it's on the die that counts.
Well, I think it is both. For a single supply via, yes. But if you
add them all up, then the ground plane has to supply (or sink) the
total of all the vias, and some of that comes from the interplane
capacitance. The via inductance will be most important at the
highest frequencies. The ground plane at slightly lower, but
still significant frequencies. At some point there is a tradeoff
between the two, and you have to figure out what that means in terms
of plane positioning.
What exactly is any of this based on?
Quote:
If you graunch off the metal
cover of an FPGA you'll see that the manufacturer has already had to add
bypass caps on the BGA substrate for this very reason. Furthermore, if
you have a PCB ground plane close to the surface and hence close to the
FPGA, the cavity between the PCB ground plane and the ground plane in
the FPGA is smaller, reducing the inductance of the vias and BGA balls
and so reducing stuff like ground bounce.
So, IMO, the disadvantages of having the planes further from your
signals and components more than outweigh the tiny gain in bypass
capacitance you gain.
I'm a bit unclear on what you are saying. You are suggesting that the
impedance of the vias is enough that you should put the planes as
close as possible to the component surface, but then you recommend
putting the decoupling caps on the back side much further away from
the component with longer vias.
To see this, you have to think of it in frequency (Fourier) space.
The switching currents have frequency components over a wide
range, with a peak somewhere near 1/(transition time) but
significant over a range of lower frequencies. The highest ones
are supplied by the internal capacitors. The next lower ones
by the ground plane itself, near the via. Lower still by the
ground plane farther away, where interplane capacitance is important.
Then there are the onboard bypass capacitors, the power supply
bypass capacitors, the power supply filter capacitors, etc.
I say better is to put your bypass caps as close as possible to the
FPGA, and maybe use puddles of copper close to the ground planes to
maximise the via and capacitor utilization. Here's an article showing
what I mean. Fig. 2.
http://www.x2y.com/bypass/mount/backside_cap.pdf
Whatever, YMMV, and I'm sure your designs work just fine. It's hard to
cock it up, but I contend that the dual ground plane design I suggest
above is nigh on impossible to go wrong with from an SI point of view,
even if you have absolutely no clue what you're doing. That's why I use it!
Yes, one common element is that most designs apply overkill in the
supply decoupling area. When an engineer uses a method and it works,
it is like the elephant protection charm... you don't see any
elephants do you, so it must be working!
I would likely not use the offset coupled planes you describe mainly
because it only works well for boards with active components on only
one side.
In Lee Ritchey's class I asked about adding caps to the package to
overcome lead inductance causing ground bounce. He showed me that the
bounce is caused by the switching currents of driving an external
signal travel in a loop and independent of any capacitance on the
package, still have to travel through the leads of the part (even if
they are only bonding leads). In fact, there is *nothing* you can do
about the series inductance of pins in a package other than fix the
package. That is why I seriously doubt that the small added
inductance of 30 mil of a via is significant in any but the highest
speed designs. But as you say, YMMV.
Yes. The problem comes with switching a large number of lines
at very close to the same time. Since they won't be at exactly
the same time (propagation delay to the pads) the highest frequency
components aren't as important as you might think. The peak
frequency of the ground current, then, will depend on how close
the transitions are to each other more than the transition rate.
The high frequency components are the only ones I care about for
ground bounce. The problem is caused by series inductance. The lower
the frequency, the lower the impact. But still, ground bounce is
largely a package problem which you can do nothing about on the board
other than make it worse.
Another really amazing thing I got from Lee's course is that there are
any number of engineers who get it wrong. I'm not talking about
typical board designers, I am talking about engineers designing chips
and packages. He has any number of examples where he was called in to
fix a problem and he told them to throw it out and start over doing it
right. In one case, they wanted to use some chip that Lee found had
too much lead impedance and would ground bounce all the noise margin
out of the logic levels. So they had to scrap the idea of using the
chip.
Rick
rickman
Guest
Sat Feb 06, 2010 10:13 am
On Feb 5, 9:24 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Quote:
Symon <symon_bre...@hotmail.com> wrote:
On 2/5/2010 9:53 PM, glen herrmannsfeldt wrote:
Yes. Actually, I believe that for the really highest frequency
components, that they are supplied by the plane itself. (Especially
as signals won't be switching at exactly the same time.)
If these highest frequencies are supplied by the planes, why do Xilinx
and Altera put capacitors on the BGA substrate? That must cost money.
Are they wrong?
OK, not quite the highest frequencies, but almost.
The highest that get through the inductance of the package and
past the internal capacitors.
I think it isn't so hard to calculate the impedance of an
infinite plane with a hole (via) as a function of frequency.
That should partly answer the question.
Two different problems. The capacitance of the power and ground
planes closely spaced is effective at frequencies well above that
where capacitors become highly inductive and the impedance rises to a
point of being useless. So any caps used inside the package are not
there to handle "the highest frequencies". To be honest, I don't know
why they would put caps inside the package unless their packages are
poorly designed, unless it is to account for poor designers... In a
discussion some time back between an engineer and a Xilinx rep about
the "recommended" decoupling caps, it was admitted that their
recommendation was overkill for most designs since there is such a
wide range of designs implemented in their parts. Reading between the
lines I would say this means they were recommending overkill for the
designers who can't figure it out for themselves. When was the last
time a design review said you had too many decoupling caps? I firmly
believe what Lee Ritchey showed me (that only a fraction of the number
of caps normally used are really needed) but I still try to use one
per power pin! Call it superstition or just lack of confidence in
myself. But no one's design failed because he used too many caps on
the power plane.
BTW, Lee Ritchey's book, "Right the First Time..." is available on CD
for $25. I recommend it. Everything I have said here is from what I
learned in his course using that book.
Rick
glen herrmannsfeldt
Guest
Sat Feb 06, 2010 1:00 pm
In comp.arch.fpga rickman <gnuarm_at_gmail.com> wrote:
(snip regarding signals crossing gaps between supply planes)
Quote:
I believe, for the most part, it doesn't do that. The capacitance
of even a single plane is high enough at the higher frequencies
that for the most part the return current doesn't have to take
the long way around.
What do you base this on? And what do you mean by the "capacitance of
even a single plane"??? What is the sound of one hand clapping?
Isn't capacitance measured between two conductors?
Consider two concentric spheres as a capacitor, and you can easily
calculate the capacitance. Now take the limit as the radius of
the outer sphere goes to infinity. The capacitance does not go
to zero. Interestingly, in the CGS (gaussian) unit system the
unit of capacitance is the centimeter. I believe that without
any factors (2, pi, etc.) it is the capacitance of a sphere to
infinity.
Otherwise, in terms of ground bounce the question is how much
does the voltage change on the pin as a function of AC current.
Q=CV I=dQ/dt=C dV/dt
Quote:
Above you said,
"The two ground planes should be well bonded with vias, so there isn't
a problem when a signal goes through a via and passes from being
referred to one ground plane to the other." How is bonding the planes
with vias useful if the current has to go all the way to a via and
back in order to follow the trace???
You have to be careful using DC thinking for AC problems.
How does (AC) current get through a capacitor? As someone else
said, for a fair frequency range the signal capacitively couples
to another plane that does cross the boundary, then back to
the first plane. The conductor is to remind the electromagnetic
wave which direction it is supposed to go.
(snip, someone wrote)
Quote:
I reject the notion of placing a power plane and a ground plane close
together in the middle of the board to get the benefit of the
inter-plane capacitance for bypassing reasons. Don't get me wrong, it
won't hurt, but IMO the amount of capacitance gained is tiny, and even
though it is a very high Q capacitor, getting the power to the die is
stymied by the inductance of the vias and BGA balls that are part of the
PDS.
I think I agree with this. The way to actually see this is to
calculate the radial propagation of the signal into the plane
from the via. The impedance (both inductance and capacitance)
will change with radial distance and frequency.
That is why Lee Ritchey's course was such an eye opener for me. There
are any number of ways you can "calculate" and theorize what happens
in power planes. But unless you verify it by testing in hardware, you
are just whistling in the dark.
I completely agree. Well, actually computers are probably about
fast enough to do the whole calculation for at least one board trace
using the actual geometry. With linearity you can compute each one
and add them together.
Quote:
Lee has done that. One test he made
that really impressed me was to show that a decoupling cap does not
need to be close to a pin to work well. If the power and ground plane
are closely spaced, the impedance is very low. If you understand
transmission lines, you will know that the current into (or out of) a
driver into the transmission line is constant until the signal reaches
the other end and depending on what load it finds, either continues
until the reflection returns to the driver (as in a series terminated
line with high impedance load) or keeps flowing as when it reaches the
decoupling cap.
Well, it has the impedance of the transmission line itself.
That depends on the inductance and capacitance of the conductors
making up the transmission line. You can consider a linear
transmission line as a sequence of series inductors and parallel
capacitors of constant value per unit length. Consider the
impedance of a finite length open ended transmission line as
a function of frequency. For some frequencies the impedance will
be very low, for others it will be very high. This property
is used for impedance matching and filtering in RF circuits.
Quote:
So if the cap is further away, the transmission line
supplies the current for decoupling until the wave front reaches the
cap. The point is that the planes have to be closely coupled for
there to be a high enough capacitance (also known as a low enough
impedance) to provide the current until the pulse reaches the cap.
Now, consider the case of a signal going into or out of a supply
plane. Now instead of the constant inductance and capacitance
per unit length you have concentric rings. The inductance decreases
and the capacitance increase with radial distance. In transmission
line terms, it is a line with the impedance decreasing with R.
Impedance decreases pretty fast, too.
A quick web search finds a paper that looks interesting on just
this problem.
http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf
The paper has much more detail than even I know, and includes
comparisons of calculations and actual boards.
Quote:
Lee actually built a board and has measurement data to show this. So
analyze away if you want, but how can you dispute measurements?
I don't dispute them. Since you don't want to build boards by
trial and error, and any measurements will only apply to the board
that they were measured on, you also want to have some understanding
of the measurements. That seems to be what the paper above does.
Quote:
If your power plane is in the middle of the board, the signal path
of these vias are longer. You don't care about the supply stiffness on
your plane, it's on the die that counts.
Well, I think it is both. For a single supply via, yes. But if you
add them all up, then the ground plane has to supply (or sink) the
total of all the vias, and some of that comes from the interplane
capacitance. The via inductance will be most important at the
highest frequencies. The ground plane at slightly lower, but
still significant frequencies. At some point there is a tradeoff
between the two, and you have to figure out what that means in terms
of plane positioning.
What exactly is any of this based on?
Well, you can calculate and/or measure the impedance of the via.
It should be pretty close to proportional to length, and decrease
with radius. Again, I am not at all against measurment.
So you have the series impedance of the via, and that parallel
impedance of the ground plane. The via, being mostly inductance,
will increase with frequency.
(snip, someone else wrote)
Quote:
I'm a bit unclear on what you are saying. You are suggesting that the
impedance of the vias is enough that you should put the planes as
close as possible to the component surface, but then you recommend
putting the decoupling caps on the back side much further away from
the component with longer vias.
To see this, you have to think of it in frequency (Fourier) space.
The switching currents have frequency components over a wide
range, with a peak somewhere near 1/(transition time) but
significant over a range of lower frequencies. The highest ones
are supplied by the internal capacitors. The next lower ones
by the ground plane itself, near the via. Lower still by the
ground plane farther away, where interplane capacitance is important.
Then there are the onboard bypass capacitors, the power supply
bypass capacitors, the power supply filter capacitors, etc.
(snip)
Quote:
The high frequency components are the only ones I care about for
ground bounce. The problem is caused by series inductance. The lower
the frequency, the lower the impact. But still, ground bounce is
largely a package problem which you can do nothing about on the board
other than make it worse.
I think I don't disagree. Still, you can't ignore the high frequencies
that aren't quite as high as the peak. That is why you need ever
bigger bypass capacitors farther out, in addition to the small and
close ones.
Quote:
Another really amazing thing I got from Lee's course is that there are
any number of engineers who get it wrong. I'm not talking about
typical board designers, I am talking about engineers designing chips
and packages. He has any number of examples where he was called in to
fix a problem and he told them to throw it out and start over doing it
right. In one case, they wanted to use some chip that Lee found had
too much lead impedance and would ground bounce all the noise margin
out of the logic levels. So they had to scrap the idea of using the
chip.
There are always tradeoffs. ICs in packages with too much lead
inductance to ever be used don't sound so useful, though. Maybe
they work in some conditions, though. Does anyone remember the 74S124?
-- glen
Symon
Guest
Sat Feb 06, 2010 2:01 pm
On 2/6/2010 8:13 AM, rickman wrote:
Quote:
To be honest, I don't know
why they would put caps inside the package
Rick
The caps are on the package because the inductance of the connecting
vias and package balls means that, no matter how good the bypassing is
on the PCB, the die on the package will have bypassing problems with
it's supply. This is why I believe the high Q bypassing from a power
plane and a ground plane doesn't help, and the layers can be arranged
differently to achieve better results by optimising other areas.
Syms.
rickman
Guest
Sat Feb 06, 2010 7:38 pm
On Feb 6, 8:01 am, Symon <symon_bre...@hotmail.com> wrote:
Quote:
On 2/6/2010 8:13 AM, rickman wrote:
To be honest, I don't know
why they would put caps inside the package
Rick
The caps are on the package because the inductance of the connecting
vias and package balls means that, no matter how good the bypassing is
on the PCB, the die on the package will have bypassing problems with
it's supply. This is why I believe the high Q bypassing from a power
plane and a ground plane doesn't help, and the layers can be arranged
differently to achieve better results by optimising other areas.
I understand what you are saying, but it does not address the problem
that the capacitors you say are used inside the chip package no longer
decouple effectively above 100 MHz or so. Certainly the noise
transients from signal switching in an FPGA extend well above 100
MHz. If the inductance of the package leads do not allow effective
connection to power/ground planes, the part will always have noise
problems.
One of the ways around the inductance of the package leads is to use
more than one lead. I believe many packages have as many as 40 or
more ground leads. So the effective impedance is then 40 times lower
than what is calculated for one pin. Has that been considered in your
analysis? Just as decoupling caps can be effective well above their
self resonant frequency where they are effectively inductors (because
the power delivery system impedance is still very low with many in
parallel), the inductors we call power pins can still be an effective
power conduit as long as the total impedance is low enough.
I keep asking you if you have done any real analysis or measurements
of what you are stating? I am no guru, but I was *very* impressed by
what Lee Ritchey said just because he has full support for just about
everything he stated in his course (except maybe that the food was
good at the Chinese restaurant).
Rick
rickman
Guest
Sat Feb 06, 2010 8:15 pm
On Feb 6, 6:00 am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
Quote:
In comp.arch.fpga rickman <gnu...@gmail.com> wrote:
(snip regarding signals crossing gaps between supply planes)
I believe, for the most part, it doesn't do that. The capacitance
of even a single plane is high enough at the higher frequencies
that for the most part the return current doesn't have to take
the long way around.
What do you base this on? And what do you mean by the "capacitance of
even a single plane"??? What is the sound of one hand clapping?
Isn't capacitance measured between two conductors?
Consider two concentric spheres as a capacitor, and you can easily
calculate the capacitance. Now take the limit as the radius of
the outer sphere goes to infinity. The capacitance does not go
to zero. Interestingly, in the CGS (gaussian) unit system the
unit of capacitance is the centimeter. I believe that without
any factors (2, pi, etc.) it is the capacitance of a sphere to
infinity.
Otherwise, in terms of ground bounce the question is how much
does the voltage change on the pin as a function of AC current.
Q=CV I=dQ/dt=C dV/dt
Ok, you have equations. I still don't believe that a ground plain all
by itself is an effective capacitor for power delivery decoupling.
Showing equations is way down the list of evidence, far below applying
equations, which is below running simulations which is far below
taking measurements. There are many, many ways to misapply equations,
so I am much more convinced by a real world measurement.
Quote:
Above you said,
"The two ground planes should be well bonded with vias, so there isn't
a problem when a signal goes through a via and passes from being
referred to one ground plane to the other." How is bonding the planes
with vias useful if the current has to go all the way to a via and
back in order to follow the trace???
You have to be careful using DC thinking for AC problems.
How does (AC) current get through a capacitor? As someone else
said, for a fair frequency range the signal capacitively couples
to another plane that does cross the boundary, then back to
the first plane. The conductor is to remind the electromagnetic
wave which direction it is supposed to go.
My bad here. I am the one saying that the planes will capacitively
couple and allow the return current to cross slots in one plane by
jumping to the other. I got your post mixed up with Symon's post
where he recommends multiple ground planes stitched together with vias
rather than capacitively coupled power/ground planes.
Quote:
(snip, someone wrote)
I reject the notion of placing a power plane and a ground plane close
together in the middle of the board to get the benefit of the
inter-plane capacitance for bypassing reasons. Don't get me wrong, it
won't hurt, but IMO the amount of capacitance gained is tiny, and even
though it is a very high Q capacitor, getting the power to the die is
stymied by the inductance of the vias and BGA balls that are part of the
PDS.
I think I agree with this. The way to actually see this is to
calculate the radial propagation of the signal into the plane
from the via. The impedance (both inductance and capacitance)
will change with radial distance and frequency.
That is why Lee Ritchey's course was such an eye opener for me. There
are any number of ways you can "calculate" and theorize what happens
in power planes. But unless you verify it by testing in hardware, you
are just whistling in the dark.
I completely agree. Well, actually computers are probably about
fast enough to do the whole calculation for at least one board trace
using the actual geometry. With linearity you can compute each one
and add them together.
Lee has done that. One test he made
that really impressed me was to show that a decoupling cap does not
need to be close to a pin to work well. If the power and ground plane
are closely spaced, the impedance is very low. If you understand
transmission lines, you will know that the current into (or out of) a
driver into the transmission line is constant until the signal reaches
the other end and depending on what load it finds, either continues
until the reflection returns to the driver (as in a series terminated
line with high impedance load) or keeps flowing as when it reaches the
decoupling cap.
Well, it has the impedance of the transmission line itself.
That depends on the inductance and capacitance of the conductors
making up the transmission line. You can consider a linear
transmission line as a sequence of series inductors and parallel
capacitors of constant value per unit length. Consider the
impedance of a finite length open ended transmission line as
a function of frequency. For some frequencies the impedance will
be very low, for others it will be very high. This property
is used for impedance matching and filtering in RF circuits.
I am aware of what a transmission line is. That is my point. The
transmission line of closely spaced planes is a very low impedance
which supplies current for the full time it takes the impulse to reach
the cap. So the spacing of the caps is not at all critical contrary
to what many will tell you.
Quote:
So if the cap is further away, the transmission line
supplies the current for decoupling until the wave front reaches the
cap. The point is that the planes have to be closely coupled for
there to be a high enough capacitance (also known as a low enough
impedance) to provide the current until the pulse reaches the cap.
Now, consider the case of a signal going into or out of a supply
plane. Now instead of the constant inductance and capacitance
per unit length you have concentric rings. The inductance decreases
and the capacitance increase with radial distance. In transmission
line terms, it is a line with the impedance decreasing with R.
Impedance decreases pretty fast, too.
A quick web search finds a paper that looks interesting on just
this problem.
http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf
The paper has much more detail than even I know, and includes
comparisons of calculations and actual boards.
What paper? I get a 404 error, page not found. Still, I don't see
the problem you seem to be describing. So the impedance drops with
increasing distance, low impedance in the power supply is a good
thing, no? Why would it dropping be a bad thing?
Lee actually has impedance vs. frequency measurements of power/ground
planes and it is pretty interesting. They don't do much below 100 MHz
or so, but beyond that the impedance is an up/down trace (all
adequately low) until it finally starts to climb above several GHz.
IIRC he explained the the sawtooth as having to do with the board
dimensions. I guess it has something to do with standing waves, but
it was some four years ago and I don't recall for sure.
I do remember that he showed some interesting interactions between the
plane capacitance and the inductance of the small sized and valued
decoupling caps. They have a resonance around 100-200 MHz I think,
which drives the impedance way up at that value. His solution was to
add other value caps which effectively move that resonance and also
damp it out to where it is acceptable. I think he showed a board
where he used a total of three different values of ceramic caps, but
only a small number of each, to get a very quiet board with a very
constant power delivery system impedance. When I took the course, I
understood how to figure it all out, but I have not had a design with
difficult power decoupling needs, so I have forgotten some of it.
Good thing I still have the book... somewhere...
Quote:
Lee actually built a board and has measurement data to show this. So
analyze away if you want, but how can you dispute measurements?
I don't dispute them. Since you don't want to build boards by
trial and error, and any measurements will only apply to the board
that they were measured on, you also want to have some understanding
of the measurements. That seems to be what the paper above does.
So the physics of each board is different??? The board Lee
constructed was a test board. I don't recall what he used for a
source of the transient, but he had spots for capacitors at a minimum
of three distances connected to the power/ground planes with optimally
short runs to the vias. He populated the caps one at a time and
measured the effectiveness finding that it dropped off barely at all
at an inch, IIRC and only moderately at a couple or three inches. The
point is that it is not really needed to put the cap right on top of
the power pin. A good power/ground plane pair is much more
important.
Quote:
If your power plane is in the middle of the board, the signal path
of these vias are longer. You don't care about the supply stiffness on
your plane, it's on the die that counts.
Well, I think it is both. For a single supply via, yes. But if you
add them all up, then the ground plane has to supply (or sink) the
total of all the vias, and some of that comes from the interplane
capacitance. The via inductance will be most important at the
highest frequencies. The ground plane at slightly lower, but
still significant frequencies. At some point there is a tradeoff
between the two, and you have to figure out what that means in terms
of plane positioning.
What exactly is any of this based on?
Well, you can calculate and/or measure the impedance of the via.
It should be pretty close to proportional to length, and decrease
with radius. Again, I am not at all against measurment.
So you have the series impedance of the via, and that parallel
impedance of the ground plane. The via, being mostly inductance,
will increase with frequency.
My point is that this is all theory. Unless you take some
measurements to verify what you are saying, you can't say it is an
accurate description of a real board and chip. Also consider that one
via is not a power supply. Vias are used in parallel giving an
effectively low impedance.
Rick
glen herrmannsfeldt
Guest
Sat Feb 06, 2010 9:01 pm
In comp.arch.fpga rickman <gnuarm_at_gmail.com> wrote:
(snip)
Quote:
My bad here. I am the one saying that the planes will capacitively
couple and allow the return current to cross slots in one plane by
jumping to the other. I got your post mixed up with Symon's post
where he recommends multiple ground planes stitched together with vias
rather than capacitively coupled power/ground planes.
Well, you want it to stay low impedance all the way down to DC.
Quote:
(snip, I wrote)
I completely agree. ?Well, actually computers are probably about
fast enough to do the whole calculation for at least one board trace
using the actual geometry. ?With linearity you can compute each one
and add them together. ?
Lee has done that. ?One test he made
that really impressed me was to show that a decoupling cap does not
need to be close to a pin to work well. ?If the power and ground plane
are closely spaced, the impedance is very low. ?If you understand
transmission lines, you will know that the current into (or out of) a
driver into the transmission line is constant until the signal reaches
the other end and depending on what load it finds, either continues
until the reflection returns to the driver (as in a series terminated
line with high impedance load) or keeps flowing as when it reaches the
decoupling cap. ?
Well, it has the impedance of the transmission line itself.
That depends on the inductance and capacitance of the conductors
making up the transmission line. ?You can consider a linear
transmission line as a sequence of series inductors and parallel
capacitors of constant value per unit length. ?Consider the
impedance of a finite length open ended transmission line as
a function of frequency. ?For some frequencies the impedance will
be very low, for others it will be very high. ?This property
is used for impedance matching and filtering in RF circuits.
I am aware of what a transmission line is. That is my point. The
transmission line of closely spaced planes is a very low impedance
which supplies current for the full time it takes the impulse to reach
the cap. So the spacing of the caps is not at all critical contrary
to what many will tell you.
I believe, though, that radial transmission lines aren't
discussed much in classes. I hadn't thought of them much until
I was replying to your post. A google search for them brought
up the paper that I tried to reference. I did the search on a
different computer and copied the link by hand. I will try again.
(Interesting all the ads that come for towing companies and
transmission repair.)
(snip)
Quote:
Now, consider the case of a signal going into or out of a supply
plane. ?Now instead of the constant inductance and capacitance
per unit length you have concentric rings. ?The inductance decreases
and the capacitance increase with radial distance. ?In transmission
line terms, it is a line with the impedance decreasing with R.
Impedance decreases pretty fast, too. ?
A quick web search finds a paper that looks interesting on just
this problem. ?
http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf
The paper has much more detail than even I know, and includes
comparisons of calculations and actual boards.
What paper? I get a 404 error, page not found. Still, I don't see
the problem you seem to be describing. So the impedance drops with
increasing distance, low impedance in the power supply is a good
thing, no? Why would it dropping be a bad thing?
OK, try again.
http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf
he seems to even include the reflections of other vias, which
seems more than is needed to me, but...
It looks like the other papers on on slot antenna design,
so he is considering PC board design in slot antenna terms.
Quote:
Lee actually has impedance vs. frequency measurements of power/ground
planes and it is pretty interesting. They don't do much below 100 MHz
or so, but beyond that the impedance is an up/down trace (all
adequately low) until it finally starts to climb above several GHz.
IIRC he explained the the sawtooth as having to do with the board
dimensions. I guess it has something to do with standing waves, but
it was some four years ago and I don't recall for sure.
With some bad luck you might get a resonance (standing wave)
where the impedance didn't stay low.
Quote:
I do remember that he showed some interesting interactions between the
plane capacitance and the inductance of the small sized and valued
decoupling caps. They have a resonance around 100-200 MHz I think,
which drives the impedance way up at that value. His solution was to
add other value caps which effectively move that resonance and also
damp it out to where it is acceptable. I think he showed a board
where he used a total of three different values of ceramic caps, but
only a small number of each, to get a very quiet board with a very
constant power delivery system impedance. When I took the course, I
understood how to figure it all out, but I have not had a design with
difficult power decoupling needs, so I have forgotten some of it.
Good thing I still have the book... somewhere...
In the old days, it might be that the tolerance kept the resonances
from being too close. The uniformity is so good now that they
will all have resonance too close together.
(snip)
Quote:
So the physics of each board is different??? The board Lee
constructed was a test board. I don't recall what he used for a
source of the transient, but he had spots for capacitors at a minimum
of three distances connected to the power/ground planes with optimally
short runs to the vias. He populated the caps one at a time and
measured the effectiveness finding that it dropped off barely at all
at an inch, IIRC and only moderately at a couple or three inches. The
point is that it is not really needed to put the cap right on top of
the power pin. A good power/ground plane pair is much more
important.
(snip)
Quote:
My point is that this is all theory. Unless you take some
measurements to verify what you are saying, you can't say it is an
accurate description of a real board and chip. Also consider that one
via is not a power supply. Vias are used in parallel giving an
effectively low impedance.
Hopefully the link is right now. He does both theory and measurement.
-- glen
glen herrmannsfeldt
Guest
Sat Feb 06, 2010 9:04 pm
Symon <symon_brewer_at_hotmail.com> wrote:
Quote:
On 2/6/2010 8:13 AM, rickman wrote:
To be honest, I don't know
why they would put caps inside the package
The caps are on the package because the inductance of the connecting
vias and package balls means that, no matter how good the bypassing is
on the PCB, the die on the package will have bypassing problems with
it's supply. This is why I believe the high Q bypassing from a power
plane and a ground plane doesn't help, and the layers can be arranged
differently to achieve better results by optimising other areas.
I think what he means is that the resonance will still be too
low even inside the package.
-- glen
Symon
Guest
Sun Feb 07, 2010 1:25 am
On 2/6/2010 7:04 PM, glen herrmannsfeldt wrote:
Quote:
Symon<symon_brewer_at_hotmail.com> wrote:
On 2/6/2010 8:13 AM, rickman wrote:
To be honest, I don't know
why they would put caps inside the package
The caps are on the package because the inductance of the connecting
vias and package balls means that, no matter how good the bypassing is
on the PCB, the die on the package will have bypassing problems with
it's supply. This is why I believe the high Q bypassing from a power
plane and a ground plane doesn't help, and the layers can be arranged
differently to achieve better results by optimising other areas.
I think what he means is that the resonance will still be too
low even inside the package.
-- glen
What resonance?
Symon
Guest
Sun Feb 07, 2010 1:37 am
On 2/6/2010 5:38 PM, rickman wrote:
Quote:
I keep asking you if you have done any real analysis or measurements
of what you are stating?
Well, this was the first time you asked IIRC, but thank you for doing
so. The answer is "For sure". I've used Hyperlynx and Spice on my
boards. I guess you have also, or else you would not be able to post
your opinions without worrying you might giving someone a bum steer.
Quote:
I am no guru,
Really?
Quote:
but I was *very* impressed by
what Lee Ritchey said just because he has full support for just about
everything he stated in his course (except maybe that the food was
good at the Chinese restaurant).
Rick
You seem to be _very_ impressed. Almost as impressed as Steve Wier.
http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4
Symon
Guest
Sun Feb 07, 2010 1:44 am
On 2/6/2010 6:15 PM, rickman wrote:
Quote:
will increase with frequency.
My point is that this is all theory. Unless you take some
measurements to verify what you are saying, you can't say it is an
accurate description of a real board and chip. Also consider that one
via is not a power supply. Vias are used in parallel giving an
effectively low impedance.
Rick
Rick,
Do you measure every resistor you put on a board. Ohm's law is a theory,
after all.
Syms xx
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