Board layout for FPGA

Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.

Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve

On Feb 4, 4:04 am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:

Thanks for the input so far, guys!

I will have two SRAM chips and one parallel EEPROM in one memory
space, and one additional RAM chip in a separate memory space so I
know for sure that that one gets its own dedicated address/control/
data lines.
I was just wondering if the signal integrity would be hurt by extra
loading in chaining up the ones that are on the same bus, but I had a
hunch that at these speeds it wouldn't be such a big problem.

Signal integrity is not normally a direct result of the "loading" of
the parts.  On most boards the effect of a pin on a bus is minimal.
If you split a run, like a fork in a river, it results in an impedance
mismatch and causes a reflection.  The end of a trace is a high
impedance which also is an impedance mismatch and causes a
reflection.  Three chips can be added to the board with trances as
short as maybe 2 inches.  This is 4 inches round trip or about half a
ns.  To avoid effects of reflection, the edge transition time should
be at least 3 ns.  That is a *slow* edge.  So expect noticeable
ringing.  As has been said, on the data and address lines, you just
need to extend the setup times to wait it out to sample the bus when
it has quieted down.  Figure three round trips or 1.5 ns extra.  But
the write enable signal should be clean.  The best way I know to do
that is to provide a separate write enable driver for each chip.  Then
you can use series impedance matching in a point to point wiring so
that the receiver does not see any effects from reflection.  Of course
this is assuming the write enable is the controlling pin when doing
writes.  Some designs use the chip select to control the write
timing.

And probably I will be using 10ns RAMs (I haven't looked at the rise/
fall times though) and keeping them physically as close as I can get
them to the FPGA.. maybe about a centimeter away, tops.
Looking at this old Digilent Spartan 3 board I have kicking around, I
don't see any termination between the FPGA and the ISSI SRAMs on
there, but each chip has its own address and data lines.. I dunno if
that's good enough to use as an example or not though.

Are you going to try to use them as fast as possible?  That can be
hard.  If you can give each chip separate drivers for all signals, may
be able to keep the traces short enough to not see any reflection
effects.  I may have muffed the math on this.  That's the trouble with
rules of thumb.  If you recall them incorrectly, it can be hard to
spot the error.  Looking at this document,

http://techcircuits.net/docs/CriticalLength.pdf

It looks like I was overly pessimistic on the length.  The rule of
thumb seems to be 1/3 instead of 1/6 so a 1 ns rise time won't cause
significant reflections, but I'm not sure about that.  On page 7 they
use an analysis that I don't agree with.  Basically, they are saying
this is the critical edge of timing and I don't think it is that clear
cut.  I say use 1/6, but you can choose your own poison.

As for the supply voltages, I'll be using a Virtex II, but this is the
first time I have started to think about implementing my own board and
thus needing to worry about power supplies, and I seemed to remember
some of my dev boards in the past having a couple or three different
regulators on board, but I didn't really think much about it. Looking
at the datasheet though, you're right, Rick, it appears that I just
need a single 1.5V supply for core voltage, and 3.3V for VCC_aux and
all of my I/O. I should have checked that and had the numbers right
before asking, sorry about that.

I would pick a newer family myself, but there is nothing wrong with a
Virtex II device.  However, a newer family will be faster, lower power
and you will likely get better support.  Of course you can overdo that
too.  If you try to use the newest family, you may not get parts for
months and the tools may be a bit buggy...  But Virtex 2???  Why not
Virtex 5 or even Virtex 4?  The Spartan 3 chips are pretty good and
have been updated quite a bit although  I don't recall which are the
latest and greatest.  I know the S3 parts are FAPP not recommended for
new designs (at least by those of us here I expect) and the S3A parts
are pretty old at this point.  Anyone, what are the newer S3x parts?

If you want to keep the power supply simple, Lattice has XP and
perhaps XP2 parts that use a single 3.3 volt supply and internally
drop it to the core voltage.

So if I need power planes for both of these voltages, do they each
need their own layer or can I arrange it carefully in one layer?

Yes, you can use one layer.  I have a very tiny board <1" x 4.5" with
no less than four power planes on one layer, +12, +5, +3.3 and an
audio 3.3.  There is another 1.8 volt plane in case I want to use an
FPGA with separate core voltage inputs, but that plane is on a
different layer shared with signal traces.  I can't stress enough the
importance of power planes in keeping switching noise down.  It is not
just a matter of adding a high frequency capacitor to the power rail,
it acts as a very low impedance transmission line connecting the
capacitors to the power pins of the chip.  It is counter intuitive,
but it actually is not so important to keep the caps so close to the
chip if you are using good power planes.  BTW, to maximize the
effectiveness of the power planes (read that as minimum impedance) you
want to have the power and ground plane as close together as
possible.  5 mils spacing should be practical and will go a long way
to doing a good job.

I found doing layout to be fun, but very intense!  Most design
requires you to go back and forth between specs and data sheets and
the schematic capture package.  Layout has some up front work getting
all the inputs and making the footprints, but then it just becomes a
really complex rubics cube with many possible solutions.  Your job is
to find one that is pretty good without spending tons of time on it.

When I did my first layout, I contacted a couple of colleges and asked
them to do a design review with me.  I was willing to pay them
consulting rates, but I was turned down.  It turned out ok in the end,
but there were a couple of things that likely would have been caught
in a review.  I am not very busy right now.  If you would like and
when you are ready, I'd be willing to go through a design review with
you without charge.  I'm pretty bored and would enjoy it.

Rick

Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

John,
I don't think I can get away with only the outer two rows of balls,
I'll probably need the two inside of that as well-- I was thinking of
breaking out the outer two on one signal layer and the inner two in
another, as suggested in the Xilinx app note I saw. It was a tight
squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
is the standard offering of the board house we're using.. it's
possible to ask for smaller, for an extra chunk of change.

To the OP, in the absence of micro-vias, I would recommend a 6 layer
board. Maybe like this:-

signal
signal
ground
ground
power/signal
signal


Everyone has their own way of doing things, but I would ask, why the
two ground planes? I would have a ground plane and a power plane in
the center with a minimum thickness between them. The spacing between
the ground/power plane and the signal plane is not so important. What
is important is the characteristic impedance. The lower the
impedance, the less it will radiate. Of course, with thin traces you
have to have the signal plane to power/ground plane very small to get
a low impedance. But if you have wide traces, you can open up the
plane spacing. Since the outer layers are on the outside of the
board, they won't be very close to inside power/ground planes. BTW,
you are aware that the power plane is just as effective as the ground
plane for determining the impedance.

Rick

BTW, you are aware that the power plane is just as effective as the
ground plane for determining the impedance.

rickman<gnuarm_at_gmail.com> writes:

BTW, you are aware that the power plane is just as effective as the
ground plane for determining the impedance.

Yes, but the OP needs to be aware that care can be required when
switching your signal trace from one layer to another. When you switch
to a layer which references the other supply rail, then the return
current has to also switch layers. If the way it has to do that is
via a decoupling cap a long way away then the current loop can be
quite large.

I got Henry Ott's new book just this morning, and he has some
discussion on p630... If you use Amazon's "search in this book"
feature from here:

http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/

and search for "Changing Reference Planes", you can see pp 630-631.

To the OP - ...and then buy it :)

Cheers,
Martin

Hi Martin,

John,
I don't think I can get away with only the outer two rows of balls,
I'll probably need the two inside of that as well-- I was thinking of
breaking out the outer two on one signal layer and the inner two in
another, as suggested in the Xilinx app note I saw. It was a tight
squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
is the standard offering of the board house we're using.. it's
possible to ask for smaller, for an extra chunk of change.

With 1mm ball pitch I use 0.5mm pads, 0.5mm vias with 0.25mm drills.

This is pretty much run of the mill for fab houses and shouldn't
add much to costs.

The lower limit for the lower end board houses (in terms of costs not
quality) tends to be around 15 mil. I don't think you can do any of
these BGAs using 15 mil vias, so the truly low end houses are likely
out anyway. It is important to choose a *good* fab house. I have
found quality to vary a *lot*.

On 2/5/2010 11:48 AM, Martin Thompson wrote:

rickman<gnu...@gmail.com> writes:

BTW, you are aware that the power plane is just as effective as the
ground plane for determining the impedance.

Yes, but the OP needs to be aware that care can be required when
switching your signal trace from one layer to another. When you switch
to a layer which references the other supply rail, then the return
current has to also switch layers. If the way it has to do that is
via a decoupling cap a long way away then the current loop can be
quite large.

I got Henry Ott's new book just this morning, and he has some
discussion on p630... If you use Amazon's "search in this book"
feature from here:

http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Hen...

and search for "Changing Reference Planes", you can see pp 630-631.

To the OP - ...and then buy it :)

Cheers,
Martin

Hi Martin,

It would appear Mr. Ott agrees that multiple ground planes with a big
centre core are a good idea, even on a four layer board. Fig. 16-15. He
must be a smart guy!! ;-)

Also, Fig. 16-16 he specifically says that

signal
signal
ground
power
signal
signal

is _not_ recommended.

Looks like he would do

signal
ground
signal
signal
ground
signal

with a thick centre core and routed powers. This way the internal signal
layers are shielded. I tend to agree. The ssggss stack I suggested
because I almost always use laser drilled micro-vias on my boards, so I
need two signal layers on the outside. Also, my enclosures do the EMC
shielding. With standard vias, sgssgs is probably better.

Cheers, Syms.

On 2/5/2010 5:40 AM, rickman wrote:

To the OP, in the absence of micro-vias, I would recommend a 6 layer
board. Maybe like this:-

signal
signal
ground
ground
power/signal
signal

Everyone has their own way of doing things, but I would ask, why the
two ground planes? I would have a ground plane and a power plane in
the center with a minimum thickness between them. The spacing between
the ground/power plane and the signal plane is not so important. What
is important is the characteristic impedance. The lower the
impedance, the less it will radiate. Of course, with thin traces you
have to have the signal plane to power/ground plane very small to get
a low impedance. But if you have wide traces, you can open up the
plane spacing. Since the outer layers are on the outside of the
board, they won't be very close to inside power/ground planes. BTW,
you are aware that the power plane is just as effective as the ground
plane for determining the impedance.

Rick

Hi Rick,

In my designs, and perhaps yours too, the power plane, such as it is, is
useless as a reference plane for the simple reason that it's chopped up
into many different pours for all the different voltages. I don't think
you are suggesting a separate layer for each separate voltage? So, there
will be slots in the plane, and every time a fast signal passes across
this slot, you'll get the thing radiating as a good slot antenna does!
You could add a bunch of bypass caps to bridge between the planes, but
there's rarely space for this with a dense BGA design. For sure, if your
planes are close together in the middle of your stack, this problem is
small, but then you need wider surface traces to get the impedance you
require.
So, I recommend multiple ground planes close to all your signals. A
thick core in the centre of the board to make up the correct thickness.
Then you can simply forget about any slot issues. Like you say, this
lets you keep the traces thin and with a lower characteristic impedance,
which is normally what you want when routing BGA FPGAs. The two ground
planes should be well bonded with vias, so there isn't a problem when a
signal goes through a via and passes from being referred to one ground
plane to the other.

I reject the notion of placing a power plane and a ground plane close
together in the middle of the board to get the benefit of the
inter-plane capacitance for bypassing reasons. Don't get me wrong, it
won't hurt, but IMO the amount of capacitance gained is tiny, and even
though it is a very high Q capacitor, getting the power to the die is
stymied by the inductance of the vias and BGA balls that are part of the
PDS. If your power plane is in the middle of the board, the signal path
of these vias are longer. You don't care about the supply stiffness on
your plane, it's on the die that counts. If you graunch off the metal
cover of an FPGA you'll see that the manufacturer has already had to add
bypass caps on the BGA substrate for this very reason. Furthermore, if
you have a PCB ground plane close to the surface and hence close to the
FPGA, the cavity between the PCB ground plane and the ground plane in
the FPGA is smaller, reducing the inductance of the vias and BGA balls
and so reducing stuff like ground bounce.
So, IMO, the disadvantages of having the planes further from your
signals and components more than outweigh the tiny gain in bypass
capacitance you gain.

I say better is to put your bypass caps as close as possible to the
FPGA, and maybe use puddles of copper close to the ground planes to
maximise the via and capacitor utilization. Here's an article showing
what I mean. Fig. 2.

http://www.x2y.com/bypass/mount/backside_cap.pdf

Whatever, YMMV, and I'm sure your designs work just fine. It's hard to
cock it up, but I contend that the dual ground plane design I suggest
above is nigh on impossible to go wrong with from an SI point of view,
even if you have absolutely no clue what you're doing. That's why I use it!

Cheers, Syms.

Yes, one common element is that most designs apply overkill in the
supply decoupling area. When an engineer uses a method and it works,
it is like the elephant protection charm... you don't see any
elephants do you, so it must be working!

worked just fine..... didn't do any noise measurements though....

A few years ago I saw a very amusing talk at London Dorkbot - in an attempt to bring old board games
up to date, James Larson created "Motherboard Operation" - players take it in turns to snip
components from a working, running PC motherboard until it stops working...

That's like Muntzing! Named after Madman Muntz.

On Feb 5, 6:42 am, Symon <symon_bre...@hotmail.com> wrote:
(snip)

In my designs, and perhaps yours too, the power plane, such as it is, is
useless as a reference plane for the simple reason that it's chopped up
into many different pours for all the different voltages. I don't think
you are suggesting a separate layer for each separate voltage? So, there
will be slots in the plane, and every time a fast signal passes across
this slot, you'll get the thing radiating as a good slot antenna does!
You could add a bunch of bypass caps to bridge between the planes, but
there's rarely space for this with a dense BGA design. For sure, if your
planes are close together in the middle of your stack, this problem is
small, but then you need wider surface traces to get the impedance you
require.

So, I recommend multiple ground planes close to all your signals. A
thick core in the centre of the board to make up the correct thickness.
Then you can simply forget about any slot issues. Like you say, this
lets you keep the traces thin and with a lower characteristic impedance,
which is normally what you want when routing BGA FPGAs. The two ground
planes should be well bonded with vias, so there isn't a problem when a
signal goes through a via and passes from being referred to one ground
plane to the other.

Below, you talk about the connecting of the power and ground plane by
spacing to be of little value and yet propose that vias are adequate
to couple multiple ground planes. I find that interesting. For a
signal passing between layers the return current would have a long
path to reach a via and back.

I reject the notion of placing a power plane and a ground plane close
together in the middle of the board to get the benefit of the
inter-plane capacitance for bypassing reasons. Don't get me wrong, it
won't hurt, but IMO the amount of capacitance gained is tiny, and even
though it is a very high Q capacitor, getting the power to the die is
stymied by the inductance of the vias and BGA balls that are part of the
PDS.

If your power plane is in the middle of the board, the signal path
of these vias are longer. You don't care about the supply stiffness on
your plane, it's on the die that counts.

If you graunch off the metal
cover of an FPGA you'll see that the manufacturer has already had to add
bypass caps on the BGA substrate for this very reason. Furthermore, if
you have a PCB ground plane close to the surface and hence close to the
FPGA, the cavity between the PCB ground plane and the ground plane in
the FPGA is smaller, reducing the inductance of the vias and BGA balls
and so reducing stuff like ground bounce.
So, IMO, the disadvantages of having the planes further from your
signals and components more than outweigh the tiny gain in bypass
capacitance you gain.

I'm a bit unclear on what you are saying. You are suggesting that the
impedance of the vias is enough that you should put the planes as
close as possible to the component surface, but then you recommend
putting the decoupling caps on the back side much further away from
the component with longer vias.

I say better is to put your bypass caps as close as possible to the
FPGA, and maybe use puddles of copper close to the ground planes to
maximise the via and capacitor utilization. Here's an article showing
what I mean. Fig. 2.

http://www.x2y.com/bypass/mount/backside_cap.pdf

Whatever, YMMV, and I'm sure your designs work just fine. It's hard to
cock it up, but I contend that the dual ground plane design I suggest
above is nigh on impossible to go wrong with from an SI point of view,
even if you have absolutely no clue what you're doing. That's why I use it!

Yes, one common element is that most designs apply overkill in the
supply decoupling area. When an engineer uses a method and it works,
it is like the elephant protection charm... you don't see any
elephants do you, so it must be working!

I would likely not use the offset coupled planes you describe mainly
because it only works well for boards with active components on only
one side.

In Lee Ritchey's class I asked about adding caps to the package to
overcome lead inductance causing ground bounce. He showed me that the
bounce is caused by the switching currents of driving an external
signal travel in a loop and independent of any capacitance on the
package, still have to travel through the leads of the part (even if
they are only bonding leads). In fact, there is *nothing* you can do
about the series inductance of pins in a package other than fix the
package. That is why I seriously doubt that the small added
inductance of 30 mil of a via is significant in any but the highest
speed designs. But as you say, YMMV.

up to date, James Larson created "Motherboard Operation" - players
take it in turns to snip components from a working, running PC
motherboard until it stops working...

This was accompanied by "PC PSU Buckaroo" - players choose and add
more and more loads to an old PC power supply until it fails....