John Larkin
Guest
Sat Aug 27, 2011 11:12 pm
On Fri, 29 Jul 2011 09:21:45 -0500, Vladimir Vassilevsky
<nospam_at_nowhere.com> wrote:
Quote:
Rob Gaddi wrote:
On 7/28/2011 5:15 PM, Vladimir Vassilevsky wrote:
Rob Gaddi wrote:
So my experience with the native bitstream compression algorithms
provided by the FPGA vendors has been that they don't actually achieve
all that much compression.
It won't be generally possible to beat vendor provided basic compression
more then by a factor of ~1.5 or so. The gain of 1.5 times wouldn't
really improve anything.
Native size is
11,875,104 bits (~1.5MB). Bitstream compresson gives me 1.35MB. 7-Zip
gives me 395kB.
Interesting.
I tried to compress JBCs from heavily used Altera Cyclone, got only
about x1.5 of compression.
As for compression algorithm, something like a bit oriented LZSS or LZW
would be easy to implement. The decompression part is trivial. If you
don't care about speed, the compression part is very simple, too. I
don't know if the further sophistication of the algorithm would do much
of a difference.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
I've done a very simple byte-oriented RLL thing on Xilinx chips and
got config files that were 20 to 40% as big as the original binaries.
Even a pretty-full chip has long runs of 0x00 and 0xFF bytes in the
bitstream. The uP code to decompress this and bang the FPGA is pretty
simple. In serial bit-bang mode, decompressing and configuring is
faster than uncompressed, because spitting out a long string of
identical bits can be done as a fast special case... just wiggle the
config clock!
John
