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Guest

Wed Apr 29, 2020 10:45 pm   



On Wednesday, 29 April 2020 21:48:55 UTC+2, Rick C wrote:
Quote:
On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is A and the other B as in your schematic.


signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;

DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;

This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.

Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?

There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended operation of the device.

The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timing concerns as the PREset on the FF.

The more info you can provide, the more help you can get.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209


You got closer Smile The design is a replacement of a custom IC used on some arcade boards.I've succesfully done reverse-engineering of this (and many other) custom ICs but I used simple TTL gates to achieve the result.This one has few logics hence I was a able to keep the same dimensions of original part by using surface mounted TTLs.But I have other with very big circuit, that's why I want to practice with CPLD.As said, for now I can only translate my TTL schematics into Quartus block diagram, I know it's not the right way, the best would be to understand the behaviour of the design and then write HDL code for it.Anyway, I tried this too under Quartus schematics, it works but the hosting hardware (the arcade board) crashes or shows other issue which are probably related to wrong timings.Right now I'm translating into Quartus schematics the latest that I reverse-engineered but sadly I run out of I/O of the EPM7128, my design is too big for it and can fit into the CPLD regardless the fact that the design use also three 2k x 8-bit static RAMs and three 74245 that I excluded from design and put them externally.But this was not enough to save I/O of the EPM7128 Smile Probably an FPGA is the best solution for this design also because you can simulate RAMs with it (I think it's not possible with CPLDs, at least memory of that size)

As for you code, I would gladly try it but, forgive my ignorancy, I don't know how to define the I/0 inside VHDL and Verilog.

Rick C
Guest

Wed Apr 29, 2020 11:45 pm   



On Wednesday, April 29, 2020 at 4:50:09 PM UTC-4, bri...@gmail.com wrote:
Quote:
On Wednesday, 29 April 2020 21:48:55 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 6:44:37 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:42:05 UTC+2, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 12:33:29 UTC+2, Rick C wrote:
On Wednesday, April 29, 2020 at 5:11:25 AM UTC-4, bri...@gmail.com wrote:
On Wednesday, 29 April 2020 06:43:32 UTC+2, Rick C wrote:
Just so you know. If the ascii art drawing looks like gibberish you need to view it in a mono-spaced font.

Here is some (untested) VHDL to implement the buffer you need for the outside world. I'm sitting here bored, so thought I'd do something useful.

-- A is an input from the FPGA/CPLD innards
-- B is output to the FPGA/CPLD innards,
-- Y is external bidir
-- OE is a high true output enable
signal A, B, Y std_logic_vector (7 downto 0);

io_buf: process(A,Y,OE) begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end process io_buf;

io_buf is just a label which is optional. Even if you give it a label adding the label at the end is always optional.

A process is not a subroutine. The list of inputs are not like the inputs/outputs of a subroutine. They are always inputs that will cause the process to "run". In VHDL2008 you can replace that list with an asterisk. If you want something modular to be used in multiple places you can make it a procedure or an entity. A procedure IS a subroutine. An entity is a module that is instantiated (connected to the rest of the circuit through a port map, i.e. a wire list).

io_buf: procedure (
signal A : in std_logic_vector(7 downto 0);
signal B : out std_logic_vector(7 downto 0);
signal Y : inout std_logic_vector(7 downto 0);
signal OE : in std_logic ) is
begin
if (OE = '1') then
Y = A;
else
Y = 'Z';
end if;

B = Y;
end procedure io_buf;


The simplest way to do this is to just use concurrent statements (the simplest type of VHDL. You don't really need the B bus at all since it is just the Y bus from the outside. So the only assignment you need is to drive the output bus to a high-Z state when you aren't driving data.

Y <= 'Z' when (OE = '0') else A;

You can add this if it is more clear

B <= Y;

Sorry if this doesn't help you. I was bored and it was useful for me to review.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Thanks for spending your time on this.
Yes, I know the two examples of the 74245 I posted are in VHDL and not in Verilog, anyway I think I can use both languages in my Quartus design.
Here is the logic diagram of my 74245 implementation (yes, I want to make this device in my CPLD design) :

http://www.mediafire.com/file/q8qspgz60nfpqum/IC74245.pdf/file

Here's the whole design, it's a simple circuit made of few TTLs gates (with a socket that plugs into the hosting hardware)

http://www.mediafire.com/file/arry2cio0l2g3aw/design.pdf/file

I don't know if you can duplicate a '245 device in a 20 pin CPLD. That will require 16 outputs and I don't think they make 20 CPLDs with 20 outputs.

Why can't you just use a 74LS245 device? They are still made. Mouser has them in stock for less than a dollar.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

I explained myself bad, sorry.I want to port into a CPLD the schematics I attached in which there is a 74245, not doing a CPLD version of the 74245.And yes, I have considered to use an external 74245 instead of implenting it in the Quartus CPLD design whereas all the remaining logics you can see in the attached schematics will be implemented in the CPLD.

I forgot.As CPLD I will use a +5V Altera EPM7128 (TQFP100) with 84 I/O and 128 macrocells.I already successfully used it in other my projects.

Ok, that is more clear. I will say the EPM7128 is very much overkill for this design, but that's ok. Better too large than too small. So the code I gave you should do the job here is an example that does the full in and out of the '245. One I/O is A and the other B as in your schematic.


signal DA, DB : std_logic_vector (7 downto 0);
signal s402_2H, s401_fi, other_ck, s601 : std_logic;
signal RD_n, s603, s602, wait_n, FF1, FF2 : std_logic;

DA <= 'Z' when (s602 or RD_n = '1') else DB;
DB <= 'Z' when (s602 or not RD_n = '1') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck))
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck))
FF2 <= FF1;
end if;
end process;

This is the logic as shown on the page. It still needs the entity boilerplate to define the I/Os for the device which are the signals on the 28 pin connector.

Can you tell me what the design does? The '245 device seems to simple connect pins on the 28 pin socket back to itself, either in one direction or the other. What plugs into the socket??? It would appear to be an MCU which makes little sense to tie 8 lines back to themselves. Or maybe you are trying to replace one of the higher complexity bus interface devices that aren't made anymore?

There are a couple of parts of the schematic that are troubling. One is the use of the PREset pin on the FF. PREset and CLR are asynchronous logic (combinational) and have very particular timing constraints which will be very different inside the CPLD and a TTL device. Without a thorough understanding of the design it is hard to know if this will work well. It is better to use the synchronous logic with separate combinational logic. That can only be done with detailed info on the intended operation of the device.

The same thing applies to the use of two inverters to create the enable on the '245 device. This is a logic noop which will only create an ill defined delay. This is hard to do in a CPLD since the tools will optimize it out. It has the same timing concerns as the PREset on the FF.

The more info you can provide, the more help you can get.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

You got closer Smile The design is a replacement of a custom IC used on some arcade boards.I've succesfully done reverse-engineering of this (and many other) custom ICs but I used simple TTL gates to achieve the result.This one has few logics hence I was a able to keep the same dimensions of original part by using surface mounted TTLs.But I have other with very big circuit, that's why I want to practice with CPLD.As said, for now I can only translate my TTL schematics into Quartus block diagram, I know it's not the right way, the best would be to understand the behaviour of the design and then write HDL code for it.Anyway, I tried this too under Quartus schematics, it works but the hosting hardware (the arcade board) crashes or shows other issue which are probably related to wrong timings.Right now I'm translating into Quartus schematics the latest that I reverse-engineered but sadly I run out of I/O of the EPM7128, my design is too big for it and can fit into the CPLD regardless the fact that the design use also three 2k x 8-bit static RAMs and three 74245 that I excluded from design and put them externally.But this was not enough to save I/O of the EPM7128 Smile Probably an FPGA is the best solution for this design also because you can simulate RAMs with it (I think it's not possible with CPLDs, at least memory of that size)

As for you code, I would gladly try it but, forgive my ignorancy, I don't know how to define the I/0 inside VHDL and Verilog.


You are obviously a very resourceful guy. You remind me of someone I worked with. He was hired by the head guy while working at a hotel restaurant, washing dishes I believe. He spoke poor English so didn't communicate well with the others. They put him on the test floor and within a few months was cranking out machines as fast as anyone. He was amazingly tenacious and took extensive notes.

I think you should take the step to using FPGAs and learning an HDL. I know VHDL and can teach you that, but many say it is harder to learn than Verilog. I don't know Verily nearly as well so can't guide you as well.

A recommended FPGA would be one of the Lattice devices. They can be bought in 100 pin QFP, well one part actually, but there are other packages you might like. 36, 48 and 72 pin QFN packages are common. The MachXO3D-4300 has everything you might want I think and comes in the QFN72 package. Internal flash so no external memory needed. 3.3 volt only power.

Lattice has free software to use with these parts.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

Rick C
Guest

Thu Apr 30, 2020 7:45 am   



With the entity declaration added the VHDL code becomes

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0);
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic;
s603, s602, wait_n : out std_logic
);
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE : std_logic;
begin

DA <= 'Z' when ((OE and not RD_n) = '0') else DB;
DB <= 'Z' when ((OE and RD_n) = '0') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
OE <= FF1 and FF2 and not s601;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck)) then
FF2 <= FF1;
end if;
end process;
end V1;

I don't have a track record of getting things right the first time. I don't see any issues with this code but that may not mean much, lol.

You can simulate the design on the computer if you know what the waveforms at IC1 should be. I assume you have a working device you can scope? If you can capture a few waveforms showing the typical cycles of operation I can generate a test bench that will simulate the design.

The signal to the enable pin on the '245 chip (G) is driven through two inverters most likely for the delay. I assume this is to allow what ever is driving the bus from the other side to turn off from the 602 signal so they aren't fighting. I created separate logic to enable the buffer from the 602 signal, but it is hard to add delays. It can be done by adding an attribute to an intermediate wire, but even then delays in CPLDs and FPGAs are partly due to routing. CPLDs have fewer routing options so less variation. Still, it may be hard to get the timing right, especially if you don't know what it needs to be.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

Caius
Guest

Thu Apr 30, 2020 10:45 am   



On Thursday, 30 April 2020 08:19:09 UTC+2, Rick C wrote:
Quote:
With the entity declaration added the VHDL code becomes

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0);
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic;
s603, s602, wait_n : out std_logic
);
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE : std_logic;
begin

DA <= 'Z' when ((OE and not RD_n) = '0') else DB;
DB <= 'Z' when ((OE and RD_n) = '0') else DA;

wait_n <= not 402_2H or s601;
s602 <= FF1 and FF2 or s601;
s603 <= s602 or not RD_n;
OE <= FF1 and FF2 and not s601;

process (other_ck, 402_2H_n) begin
if (402_2H = '1') then
FF1 <= '1';
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi;
end if;

if (falling_edge(other_ck)) then
FF2 <= FF1;
end if;
end process;
end V1;

I don't have a track record of getting things right the first time. I don't see any issues with this code but that may not mean much, lol.

You can simulate the design on the computer if you know what the waveforms at IC1 should be. I assume you have a working device you can scope? If you can capture a few waveforms showing the typical cycles of operation I can generate a test bench that will simulate the design.

The signal to the enable pin on the '245 chip (G) is driven through two inverters most likely for the delay. I assume this is to allow what ever is driving the bus from the other side to turn off from the 602 signal so they aren't fighting. I created separate logic to enable the buffer from the 602 signal, but it is hard to add delays. It can be done by adding an attribute to an intermediate wire, but even then delays in CPLDs and FPGAs are partly due to routing. CPLDs have fewer routing options so less variation. Still, it may be hard to get the timing right, especially if you don't know what it needs to be.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209


Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal

I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

Johann Klammer
Guest

Thu Apr 30, 2020 3:45 pm   



On 04/28/2020 08:24 PM, briccus_at_gmail.com wrote:
Quote:
Hi all,
I'm new to Verilog (although I've been designing and repairing electronics since many years).Not being yet familiar with coding I'm porting to Quartus schematics block some designs of mine using the examples (primitives) in the library.There are a couple of designs with bidirectional bus (made by the 74LS245 transceiver) hence I was wondering how to accomplish this in Verilog.Here are snippets of schematics:

https://i.postimg.cc/HLDFnmFZ/bidir.jpg

https://i.postimg.cc/XvfMVrs7/bidir-2.jpg

Any help or suggestion is appreciated.Thanks in advance.

For gate level modelling the bufif0/1 and notif0/1 primitives exist.


Rick C
Guest

Thu Apr 30, 2020 9:45 pm   



On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:
Quote:

Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal


I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin

DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;

wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;

process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;

if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;

This one at least has no syntax errors.


> I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?


Quote:
As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board


Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.

I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.

There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in your design.

https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#

I haven't used Gowin's tools yet. I expect they work adequately.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

Caius
Guest

Thu Apr 30, 2020 11:45 pm   



On Thursday, 30 April 2020 21:56:22 UTC+2, Rick C wrote:
Quote:
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:

Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal

I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin

DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;

wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;

process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;

if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;

This one at least has no syntax errors.


I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?


As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.

I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.

There's also an interesting board with a Gowin part (new Chinese company).. It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in your design.

https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#

I haven't used Gowin's tools yet. I expect they work adequately.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209


I tried the code, the hosting hardware (the arcade board) is watchdogging and keeps resetting in an endless loop.Just to be sure we used same pin labeling, is your DB0-DB7 the DB0-DB7 of my schematics (and your DA0-DA7 my D0-D7)?
Anywyay, thanks for wasting your time with this thing (and indeed you called it 'Thing'...)
Thanks also for the links of the FPGA dev boards, I gonna to purchase some to play with :)

P.S.
I think the labeling of my schematics come from the schematics of the arcade board but I can't exactly remember now.I'll check and let you know.

Rick C
Guest

Fri May 01, 2020 1:45 am   



On Thursday, April 30, 2020 at 6:24:14 PM UTC-4, Caius wrote:
Quote:
On Thursday, 30 April 2020 21:56:22 UTC+2, Rick C wrote:
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:

Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal

I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin

DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;

wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;

process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;

if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;

This one at least has no syntax errors.


I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?


As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.

I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.

There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in your design.

https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#

I haven't used Gowin's tools yet. I expect they work adequately.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

I tried the code, the hosting hardware (the arcade board) is watchdogging and keeps resetting in an endless loop.Just to be sure we used same pin labeling, is your DB0-DB7 the DB0-DB7 of my schematics (and your DA0-DA7 my D0-D7)?


Good thing you asked. DA and DB in my code correspond to the A and B buses on the '245 chip. So DA in the code is DB on your schematic and DB in the code is D on your schematic.


Quote:
Anywyay, thanks for wasting your time with this thing (and indeed you called it 'Thing'...)
Thanks also for the links of the FPGA dev boards, I gonna to purchase some to play with :)

P.S.
I think the labeling of my schematics come from the schematics of the arcade board but I can't exactly remember now.I'll check and let you know.


I'm just looking for meaning in any of the signal names. Do you have a schematic of the arcade board??? That would help tremendously... at least if the chips aren't all Thing_1 and Thing_2.

You know I'm going to expect you to name your first born after me, right?

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

Caius
Guest

Fri May 01, 2020 11:45 am   



On Friday, 1 May 2020 01:47:39 UTC+2, Rick C wrote:
Quote:
On Thursday, April 30, 2020 at 6:24:14 PM UTC-4, Caius wrote:
On Thursday, 30 April 2020 21:56:22 UTC+2, Rick C wrote:
On Thursday, April 30, 2020 at 5:36:44 AM UTC-4, Caius wrote:

Thanks for your words, I only hope to not end up washing dishes ahahaha
Anyway I tried to compile your code but unsuccessfully because Quartus complains about wrong syntax :

Error (10500): VHDL syntax error at thing.vhd(20) near text "or"; expecting ";"
Error (10500): VHDL syntax error at thing.vhd(24) near text "4022"; expecting an identifier, or a string literal

I did give a disclaimer about my getting things right the first go. I found four errors, names can't begin with a numeric digit, I used -> instead of => in the aggregate (others =>), read an output and forgot required parens in a couple of places.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;
begin

DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;

wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= (not s601) and FF1 and FF2 ;
s602 <= s602_int ;

process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;

if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;

This one at least has no syntax errors.


I can provide you signal analyzing with my digital oscilloscope (I guess of the outputs and clock signals or the whole bus syncronized with other signals?).

All of the control signals would be good. One bit of each bus might help understand when it goes tristate. Are there memory cycles going on? I/O cycles? Where did the names 602, 603, etc. come from? Yours or on the unit?


As for FPGA practicing I spotted this cheap dev board to play with :

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

Might be good. Needs a programming cable. I see one on eBay under $20 with a cable. https://www.ebay.com/itm/222882868419 Very slow shipping.

I would suggest you look at the TinyFPGA boards. The BX includes the programmer on the module. It's $40, but you can mount the module directly on your board. https://tinyfpga.com/ There's a number of Lattice based dev boards about.

There's also an interesting board with a Gowin part (new Chinese company). It's got a lot on it. Just $11 including shipping. Interfaces to a $17, 5 inch color LCD display. Not bad if you can use that. Otherwise it is small enough to be used in your design.

https://www.ebay.com/i/184024583893?chn=ps&var=691716640114#

I haven't used Gowin's tools yet. I expect they work adequately.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

I tried the code, the hosting hardware (the arcade board) is watchdogging and keeps resetting in an endless loop.Just to be sure we used same pin labeling, is your DB0-DB7 the DB0-DB7 of my schematics (and your DA0-DA7 my D0-D7)?

Good thing you asked. DA and DB in my code correspond to the A and B buses on the '245 chip. So DA in the code is DB on your schematic and DB in the code is D on your schematic.


Anywyay, thanks for wasting your time with this thing (and indeed you called it 'Thing'...)
Thanks also for the links of the FPGA dev boards, I gonna to purchase some to play with :)

P.S.
I think the labeling of my schematics come from the schematics of the arcade board but I can't exactly remember now.I'll check and let you know.

I'm just looking for meaning in any of the signal names. Do you have a schematic of the arcade board??? That would help tremendously... at least if the chips aren't all Thing_1 and Thing_2.

You know I'm going to expect you to name your first born after me, right?

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209


I promise I will name my first son with your name Smile (Riccardo in italian language, a nice name)

I reviewed the pin assignement and tried again your code, it works fine in a board but not in another.
The one in which it works is Green Beret, full schematics here (the IC is labeled '501' at location '3C')

http://pdf.textfiles.com/manuals/ARCADE/A-J/Green%20Beret%20[Schematics]%20[English].pdf

The board that doesn't work with your code (it's watchdogging) is Time Pilot, schematics here (the IC is the one labeled 'C3' @IC2 on top left of PDF)

http://pdf.textfiles.com/manuals/ARCADE/S-Z/Time%20Pilot%20(CPU%20600dpi)%20[Schematics]%20[English].pdf


Thanks again for spending your time with this.

Rick C
Guest

Fri May 01, 2020 2:45 pm   



On Friday, May 1, 2020 at 6:04:05 AM UTC-4, Caius wrote:
Quote:

I reviewed the pin assignement and tried again your code, it works fine in a board but not in another.
The one in which it works is Green Beret, full schematics here (the IC is labeled '501' at location '3C')

http://pdf.textfiles.com/manuals/ARCADE/A-J/Green%20Beret%20[Schematics]%20[English].pdf


I only see one part that might be the "patch board" for the custom chip, it's labeled "501" and "5C", not "3C".

Now I'm confused about the buses. In the Green Beret schematic bus DB is on pins numbered 1 to 8 and bus D is on pins numbered 20 to 27. That is opposite your schematic for the internals. I suppose that was an error made by the original designer of the "patch" board who had it working, so all is really ok. The Time Pilot board has the buses labeled the other way I just realized, so that's the source of the problem.

Pins 15 and 16 are not shown for the Green Beret. Your drawing shows them not connected. That seems ok.

Green Beret shows pin 18 going to the 200 pin mystery chip as an input. Any info on that guy? The signal is labeled "BUS".

In your schematic pin 17 is "603". The Green Beret has nothing connected if I understand the notation. Please confirm. On Time Pilot this is F2 and pin 12 connects to F3. I can't find the source of either. On Green Beret pin 12 is CS501 from the giant mystery chip.

Pin 9 goes to the 2H signal on the Green Beret again from the giant mystery chip. On Time Pilot it is G2 from IC3, a small mystery chip. Also pin 10, G1 on Time Pilot is X15 on Green Beret, the CPU clock inverted. Pin 11 is the chip clock ~6 MHz on Time Pilot, from the giant mystery chip on Green Beret.

On both boards pin 19 is Wait_n and 13 is RD_n from the Z80.

I think that is everything I can figure out from the schematics. I guess I expected more TTL.


Quote:
The board that doesn't work with your code (it's watchdogging) is Time Pilot, schematics here (the IC is the one labeled 'C3' @IC2 on top left of PDF)

http://pdf.textfiles.com/manuals/ARCADE/S-Z/Time%20Pilot%20(CPU%20600dpi)%20[Schematics]%20[English].pdf


Thanks again for spending your time with this.


BTW, I happened to find this...

https://www.jammarcade.net/28-pin-cpld-replacement/

I guess using a CPLD/FPGA is an obvious idea. No details on what went inside the chip. It's from 2016, so maybe you can still contact the guy? The article talks about slowing the slew rate on the I/Os and the glitches were gone. Not sure that will work, but worth a try.

BTW, I might have made a logical mistake in the VHDL file.

OE <= (not s601) and FF1 and FF2 ;

Should be...

OE <= not s602_int ;

I was trying to write the same function as 602 but in a different way so the tools might not combine them (it's about the delay thing through the two inverters). But I don't think it will work and I goofed up the equation anyway. This way matches my use of a high true output enable for OE.

Delays are all in the chips in TTL, but in PLDs the delays happen in many parts of the circuit inside.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

Caius
Guest

Fri May 01, 2020 3:45 pm   



Quote:

I only see one part that might be the "patch board" for the custom chip, it's labeled "501" and "5C", not "3C".


3C is the location of the same '501' custom IC on the Time Pilot schematics
Quote:

Now I'm confused about the buses. In the Green Beret schematic bus DB is on pins numbered 1 to 8 and bus D is on pins numbered 20 to 27. That is opposite your schematic for the internals. I suppose that was an error made by the original designer of the "patch" board who had it working, so all is really ok. The Time Pilot board has the buses labeled the other way I just realized, so that's the source of the problem.


Take my Kicad schematics as reference , some board use the entire functionality of the custom IC, some not.My TTL implementation is complete and has beeen succesfully tested on all boards.Labels may vary on different boards.
Quote:

Pins 15 and 16 are not shown for the Green Beret. Your drawing shows them not connected. That seems ok.


These pins are used in other boards
Quote:

Green Beret shows pin 18 going to the 200 pin mystery chip as an input. Any info on that guy? The signal is labeled "BUS".

In your schematic pin 17 is "603". The Green Beret has nothing connected if I understand the notation. Please confirm. On Time Pilot this is F2 and pin 12 connects to F3. I can't find the source of either. On Green Beret pin 12 is CS501 from the giant mystery chip.


Again, refer to my Kicad schematics for the reasons I explained above.
Quote:

Pin 9 goes to the 2H signal on the Green Beret again from the giant mystery chip. On Time Pilot it is G2 from IC3, a small mystery chip. Also pin 10, G1 on Time Pilot is X15 on Green Beret, the CPU clock inverted. Pin 11 is the chip clock ~6 MHz on Time Pilot, from the giant mystery chip on Green Beret.

On both boards pin 19 is Wait_n and 13 is RD_n from the Z80.

I think that is everything I can figure out from the schematics. I guess I expected more TTL.


This '501' custom ICs can have different labels but it accomplishes same functions on all board at the end.
Quote:



BTW, I happened to find this...

https://www.jammarcade.net/28-pin-cpld-replacement/

I guess using a CPLD/FPGA is an obvious idea. No details on what went inside the chip. It's from 2016, so maybe you can still contact the guy? The article talks about slowing the slew rate on the I/Os and the glitches were gone. Not sure that will work, but worth a try.


I use a similar CPLD board made by me.That replacement on JAMMArcade site must be programmed with your code.Anyway, I already enable the SLOW SLEW RATE with your code but it didn't help.
Quote:

BTW, I might have made a logical mistake in the VHDL file.

OE <= (not s601) and FF1 and FF2 ;

Should be...

OE <= not s602_int ;

I was trying to write the same function as 602 but in a different way so the tools might not combine them (it's about the delay thing through the two inverters). But I don't think it will work and I goofed up the equation anyway. This way matches my use of a high true output enable for OE.

Delays are all in the chips in TTL, but in PLDs the delays happen in many parts of the circuit inside.


OK, I'll try this code fix, thanks.
Quote:

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209


Rick C
Guest

Fri May 01, 2020 3:45 pm   



On Friday, May 1, 2020 at 10:00:37 AM UTC-4, Caius wrote:
Quote:

I only see one part that might be the "patch board" for the custom chip, it's labeled "501" and "5C", not "3C".

3C is the location of the same '501' custom IC on the Time Pilot schematics

Now I'm confused about the buses. In the Green Beret schematic bus DB is on pins numbered 1 to 8 and bus D is on pins numbered 20 to 27. That is opposite your schematic for the internals. I suppose that was an error made by the original designer of the "patch" board who had it working, so all is really ok. The Time Pilot board has the buses labeled the other way I just realized, so that's the source of the problem.

Take my Kicad schematics as reference , some board use the entire functionality of the custom IC, some not.My TTL implementation is complete and has beeen succesfully tested on all boards.Labels may vary on different boards..

Pins 15 and 16 are not shown for the Green Beret. Your drawing shows them not connected. That seems ok.

These pins are used in other boards

Green Beret shows pin 18 going to the 200 pin mystery chip as an input. Any info on that guy? The signal is labeled "BUS".

In your schematic pin 17 is "603". The Green Beret has nothing connected if I understand the notation. Please confirm. On Time Pilot this is F2 and pin 12 connects to F3. I can't find the source of either. On Green Beret pin 12 is CS501 from the giant mystery chip.

Again, refer to my Kicad schematics for the reasons I explained above.

Pin 9 goes to the 2H signal on the Green Beret again from the giant mystery chip. On Time Pilot it is G2 from IC3, a small mystery chip. Also pin 10, G1 on Time Pilot is X15 on Green Beret, the CPU clock inverted. Pin 11 is the chip clock ~6 MHz on Time Pilot, from the giant mystery chip on Green Beret.

On both boards pin 19 is Wait_n and 13 is RD_n from the Z80.

I think that is everything I can figure out from the schematics. I guess I expected more TTL.

This '501' custom ICs can have different labels but it accomplishes same functions on all board at the end.



BTW, I happened to find this...

https://www.jammarcade.net/28-pin-cpld-replacement/

I guess using a CPLD/FPGA is an obvious idea. No details on what went inside the chip. It's from 2016, so maybe you can still contact the guy? The article talks about slowing the slew rate on the I/Os and the glitches were gone. Not sure that will work, but worth a try.

I use a similar CPLD board made by me.That replacement on JAMMArcade site must be programmed with your code.Anyway, I already enable the SLOW SLEW RATE with your code but it didn't help.

BTW, I might have made a logical mistake in the VHDL file.

OE <= (not s601) and FF1 and FF2 ;

Should be...

OE <= not s602_int ;

I was trying to write the same function as 602 but in a different way so the tools might not combine them (it's about the delay thing through the two inverters). But I don't think it will work and I goofed up the equation anyway. This way matches my use of a high true output enable for OE.

Delays are all in the chips in TTL, but in PLDs the delays happen in many parts of the circuit inside.

OK, I'll try this code fix, thanks.


I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.

That's ok for now. Let's see if the code change helps or breaks it.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

Caius
Guest

Fri May 01, 2020 4:45 pm   



On Friday, 1 May 2020 17:29:55 UTC+2, Caius wrote:
Quote:
On Friday, 1 May 2020 16:24:23 UTC+2, Rick C wrote:


I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.

Yes, sorry for upsetting you.Although I'm into electronics since many years I still have to fully understand it, that's the key to do electronics, I know.It's like a gorgeous woman, it bewitches and takes you but, like all beautiful things, it's dangerous if you don't have full control over it :)



That's ok for now. Let's see if the code change helps or breaks it.

And you did it!It's working fine now also on Time Pilot PCB, no more watchdogging or other issues, congratulations.Just a question : you inverted in your latest code fix the /OE signal only one time whereas in my TTL schematics it's done twice (to produce some delay as you said).Is this still correct given that the /OE is an active LOW signal?

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209


Actually there are still some litte graphical glitches on Time Pilot (on Green Beret it runs perfecty).I get the same glitches when I ported my TTL schematics in Quartus block diagram hence this is most likely something strictly related to CPLD I'm using, it's too fast for this old hardware.I'm gonna to see if the SLEW RATE can help.I think your code if fine.

Caius
Guest

Fri May 01, 2020 4:45 pm   



On Friday, 1 May 2020 16:24:23 UTC+2, Rick C wrote:

Quote:

I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.


Yes, sorry for upsetting you.Although I'm into electronics since many years I still have to fully understand it, that's the key to do electronics, I know.It's like a gorgeous woman, it bewitches and takes you but, like all beautiful things, it's dangerous if you don't have full control over it :)



> That's ok for now. Let's see if the code change helps or breaks it.

And you did it!It's working fine now also on Time Pilot PCB, no more watchdogging or other issues, congratulations.Just a question : you inverted in your latest code fix the /OE signal only one time whereas in my TTL schematics it's done twice (to produce some delay as you said).Is this still correct given that the /OE is an active LOW signal?
Quote:

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209


Rick C
Guest

Fri May 01, 2020 8:45 pm   



On Friday, May 1, 2020 at 11:29:55 AM UTC-4, Caius wrote:
Quote:
On Friday, 1 May 2020 16:24:23 UTC+2, Rick C wrote:


I'm trying to understand what the circuit does. So when I ask about the signals and what they come from telling me to look at your design isn't giving me any info I don't already have.

Yes, sorry for upsetting you.Although I'm into electronics since many years I still have to fully understand it, that's the key to do electronics, I know.It's like a gorgeous woman, it bewitches and takes you but, like all beautiful things, it's dangerous if you don't have full control over it Smile


No, I'm not upset. This is all fun. One of the things I like is debugging.. It's like solving a mystery. I've designed electronics for decades, but the time I most enjoyed was working on the test floor of a company building super computers. In some ways anyone can design stuff, but it is very hard to make bad units good.


Quote:
That's ok for now. Let's see if the code change helps or breaks it.

And you did it!It's working fine now also on Time Pilot PCB, no more watchdogging or other issues, congratulations.Just a question : you inverted in your latest code fix the /OE signal only one time whereas in my TTL schematics it's done twice (to produce some delay as you said).Is this still correct given that the /OE is an active LOW signal?


The difference is in my design the signal OE rather than /OE. But what is important is the polarity of the OE signal and in the EPM7128 it is /OE, so the exact same signal as s602 like in the TTL design. That my design uses OE doesn't matter because they are all logical and the tool knows what polarity the hardware is. So it adds an inverter to OE to make it /OE inside the device. So too many inverters by one to make it different from s602.

I can't think of a way to force the tool to give us an extra logic level unless the synthesis attribute keep is used.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Thing is
port (
DA, DB : inout std_logic_vector (7 downto 0) ;
s402_2H, s401_fi, other_ck, s601, RD_n : in std_logic ;
s603, s602, wait_n : out std_logic ) ;
end Thing ;

architecture V1 of Thing is
signal FF1, FF2, OE, s602_int : std_logic ;

attribute keep: boolean;
attribute keep of OE: signal is true;
begin

DA <= (others => 'Z') when ((OE and (not RD_n)) = '0') else DB ;
DB <= (others => 'Z') when ((OE and RD_n) = '0') else DA ;

wait_n <= (not s402_2H) or s601 ;
s602_int <= (FF1 and FF2) or s601 ;
s603 <= (not RD_n) or s602_int ;
OE <= not s602_int ;
s602 <= s602_int ;

process (other_ck, s402_2H) begin
if (s402_2H = '1') then
FF1 <= '1' ;
elsif (rising_edge(other_ck)) then
FF1 <= s401_fi ;
end if ;

if (falling_edge(other_ck)) then
FF2 <= FF1 ;
end if ;
end process ;
end V1 ;


Now the tool will force the use of an additional logic element to create OE and since the tristate enable on the output buffer is /OE it will add a second layer of superfluous logic. The two layers of logic will give some delay (~5 nS) but not nearly as much as two LS inverters. If the above code does not work we can try routing the signal out through an I/O pin and back in another pin. Do you have two I/O pins you can connect? That will let us tailor the delay using the slew rate control.

I just wish I could see the timing of the control signals. That could help a lot.

--

Rick C.

++- Get 1,000 miles of free Supercharging
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