Basic question with tran gates

If  I am using debug during the simultion of the following RTL, and
there forcing a vallue using PLI on the signal inpad inside the
tran_mod, Should this be propagated to the wire pad.
I am a software engineer and  have basic understanding of  bheavioral
and other gate level modeling, But switch level modelling is still
elusive to me. Can some one please help

module top;
wire inpad ;
wire pad;
reg i ,j;
assign inpad = i;
assign pad = j;

tran_mod t1 (inpad,pad);
initial
begin
#1 i = 1;
#1 j = 0;
#10
i= 0;
j = 1;
end
endmodule

module tran_mod (inout inpad, inout pad);
tran t1(inpad,pad);

initial
$monitor( inpad, pad);

bot b1(inpad);
endmodule

module bot(inout b1);
always @(b1)
$display("the valuepropagation comes here\n");
endmodule

On Jan 19, 11:52 pm, parag <parag.p...@gmail.com> wrote:
If I am using debug during the simultion of the following RTL, and
there forcing a vallue using PLI on the signal inpad inside the
tran_mod, Should this be propagated to the wire pad.
I am a software engineer and have basic understanding of bheavioral
and other gate level modeling, But switch level modelling is still
elusive to me. Can some one please help

I also want to know whether it is possible to have two different
values in the wires that are connected via a tran gate
IN the above example

parag wrote:
On Jan 19, 11:52 pm, parag <parag.p...@gmail.com> wrote:
If  I am using debug during the simultion of the following RTL, and
there forcing a vallue using PLI on the signal inpad inside the
tran_mod, Should this be propagated to the wire pad.
I am a software engineer and  have basic understanding of  bheavioral
and other gate level modeling, But switch level modelling is still
elusive to me. Can some one please help

Given what you have shown I would say no. Actually given what you have
shown I would expect 'bx on both nets most of the time. Since the drive
strength is the same (strong) on both sides this should resolve to 'bx
if the two drivers have different values. The force will set the net it
is driving, but the other side of the tran will resolve to 'bx unless
the force and the other driver are driving the same value. You could
also get different results if you forced each side of the tran or used a
driver with a supply driver strength. If you lowered the drive strength
of the two drivers I would expect the force to propagate. The tran
devices are tricky and very under documented. You should make sure you
know exactly why you are using them and if you don't have a good reason
use something else.

I also want to know whether it is possible to have two different
values in the wires that are connected via a tran gate
IN the above example

Answered above.

I hope this help and is correct, but given the obscure nature of this
don't count on my view being 100% correct.

Cary

Thanks a lot Cary
I was of the opinion that the current value of the tran gate itself
was also a determinant of resolved value the wires on both side
I am still a bit confused about the same

Thanks a lot Cary
I was of the opinion that the current value of the tran gate itself
was also a determinant of resolved value the wires on both side
I am still a bit confused about the same

parag wrote:
Thanks a lot Cary
I was of the opinion that the current value of the tran gate itself
was also a determinant of resolved value the wires on both side
I am still a bit confused about the same

No, the tran device has no state. It is as if you wired the end
points together. Another way of saying this: it is level sensitive.

So the two endpoints of a tran are resolved with normal Verilog
strength resolution rules.

On Feb 3, 2:04 am, "Cary R." <no-s...@host.spam> wrote:
Stephen Williams wrote:
parag wrote:
Thanks a lot Cary
I was of the opinion that the current value of the tran gate itself
was also a determinant of resolved value the wires on both side
I am still a bit confused about the same
No, the tran device has no state. It is as if you wired the end
points together. Another way of saying this: it is level sensitive.
So the two endpoints of a tran are resolved with normal Verilog
strength resolution rules.
Except a supply strength is reduced to strong when it passes through a tran.

Cary

isnt that the case with the mos switch (strength reduction switches )

Stephen Williams wrote:
parag wrote:
Thanks a lot Cary
I was of the opinion that the current value of the tran gate itself
was also a determinant of resolved value the wires on both side
I am still a bit confused about the same

No, the tran device has no state. It is as if you wired the end
points together. Another way of saying this: it is level sensitive.

So the two endpoints of a tran are resolved with normal Verilog
strength resolution rules.

Except a supply strength is reduced to strong when it passes through a tran.

Cary