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Guest

Wed Feb 24, 2016 8:00 pm

Hi all,

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys

the flash Storage Controller and the Error Correction Code on FPGA. The

Software is C++, yet the firmware is VERILOG. It is my first time

working with Verilog and for now I only want a small trick in order to

test a hypothesis.

My question is:

Let's say I have

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can

I do this trick in the assign?

parameter PARITY_ONE = 1;

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

best,

Elena

Guest

Wed Feb 24, 2016 8:39 pm

In article <f40a0e2b-eaab-4bd9-8c49-4f2dbbf6ef37_at_googlegroups.com>,

Elena Cososchi <mcososchi_at_gmail.com> wrote:

Hi all,

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys

the flash Storage Controller and the Error Correction Code on FPGA. The

Software is C++, yet the firmware is VERILOG. It is my first time

working with Verilog and for now I only want a small trick in order to

test a hypothesis.

My question is:

Let's say I have

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can

I do this trick in the assign?

parameter PARITY_ONE = 1;

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys

the flash Storage Controller and the Error Correction Code on FPGA. The

Software is C++, yet the firmware is VERILOG. It is my first time

working with Verilog and for now I only want a small trick in order to

test a hypothesis.

My question is:

Let's say I have

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can

I do this trick in the assign?

parameter PARITY_ONE = 1;

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

Elena,

comp.lang.verilog would be a better place to ask!

In any event, yes this will work fine.

Regards,

Mark

Guest

Thu Feb 25, 2016 2:55 am

Elena Cososchi wrote:

Hi all,

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys

the flash Storage Controller and the Error Correction Code on FPGA. The

Software is C++, yet the firmware is VERILOG. It is my first time

working with Verilog and for now I only want a small trick in order to

test a hypothesis.

My question is:

Let's say I have

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can

I do this trick in the assign?

parameter PARITY_ONE = 1;

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

best,

Elena

I am newly working with Cosmos OpenSSD, a real SSD Board that deploys

the flash Storage Controller and the Error Correction Code on FPGA. The

Software is C++, yet the firmware is VERILOG. It is my first time

working with Verilog and for now I only want a small trick in order to

test a hypothesis.

My question is:

Let's say I have

assign nxt_parity[i] = cur_parity[i-1];

I want nxt_parity vector to have only 1s, independent of cur_parity. Can

I do this trick in the assign?

parameter PARITY_ONE = 1;

assign nxt_parity[i] = ((cur_parity[i-1])||(PARITY_ONE));

Thank you very much for any hint you may provide!

best,

Elena

Perhaps you really wanted a mux like:

assign nxt_parity[i] = PARITY_ONE ? 1 : cur_parity[i-1];

This is equivalent to what you wrote If nxt_parity[i]

is a single bit. If nxt_parity is an array like:

wire [7:0] nxt_parity [0:7];

Then the two are not equivalent. As you wrote it, if either

cur_parity[i-1] is non-zero or PARITY_ONE is non-zero, then

nxt_parity[i] will take the value 1, regardless of the number

of bits it has.

If you want to OR *each* bit of a vector with PARITY_ONE,

you could replicate PARITY_ONE to the width of the vector like:

parameter WIDTH = 8;

parameter DEPTH = 1024;

parameter PARITY_ONE = 1;

wire [WIDTH-1:0] nxt_parity [0:DEPTH-1];

wire force_parity = PARITY_ONE;

assign nxt_parity[i] = cur_parity[i-1] | {WIDTH{force_parity}};

equivalent to:

assign nxt_parity[i] = PARITY_ONE ? {WIDTH{1'b1}} : cur_parity[i-1];

--

Gabor

Guest

Fri Feb 26, 2016 3:18 pm

VHDL only please. :)

If you really need a mux:

nxt_parity(i) <= '1' when PARITY_ONE else cur_parity(i-1);

If you want to force nxt_parity to all '1's, which means all bits are tied to HIGH regardless of any other signals:

nxt_parity <= (others => '1');

-daniel

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