Backplanes and daughter boards. Connecting the same signal l

Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.

None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.

We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.

Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.

Help is appreciated! Thanks.

"M. Hamed" <mhelshou_at_hotmail.com> wrote in message
news:40703d15-7a81-4a50-939e-accabe44b6be_at_k1g2000prl.googlegroups.com...
Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.

None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.

We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.

Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.

Help is appreciated! Thanks.

Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for
the backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each
line and at each end of the backplane (or you can use active termination).
VME also defines the driver characteristics, and you can buy chips
specifically for VME. There should only be one load on each signal, and
the drivers mounted close to the connectors to minimise stub lengths
(which are 3 row DIN41612 type for standard VME16 and VME32).

Mark.

Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board.

Q#1: How many daughters?

Q#2: Are you sure they can't be serially communicated.

Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each line
and at each end of the backplane (or you can use active termination). VME
also defines the driver characteristics, and you can buy chips specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3 row
DIN41612 type for standard VME16 and VME32).

Mark.

On Aug 11, 5:03 pm, "markp" <map.nos...@f2s.com> wrote:
Is it a parallel bus or serial? What bandwidth do you need? Would RS485 do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each line
and at each end of the backplane (or you can use active termination). VME
also defines the driver characteristics, and you can buy chips specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3 row
DIN41612 type for standard VME16 and VME32).

Mark.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

The design I was thinking of is probably a backplane that has an on-
board controller. The controller would receive commands from a PC
through USB or serial. Each daughter board would be enabled one at a
time using relays. Perhaps using MOSFETs for turning on power and
relays for routing clock and data. Once a daughter board is enabled,
another on-daughter-board controller (instructed by the main-board
controller) would route the signals to each chip perhaps using analog
switches or another set of relays. I don't know if this is too much
from a signal integrity standpoint.

The serial bandwidth is somewhere from 5 MHz to 20 MHz, i.e. each
serial clock would take from 50 ns to 200ns. The faster the better but
we could make it slower if signal integrity problems are unsolvable at
the high speed.

Does that sound reasonable? I'm also not sure how we would go about
characterizing capacitances, impedances, and such.

On Wed, 11 Aug 2010 17:30:07 -0700 (PDT), "M. Hamed"
mhelshou_at_hotmail.com> wrote:

On Aug 11, 5:03 pm, "markp" <map.nos...@f2s.com> wrote:
Is it a parallel bus or serial? What bandwidth do you need? Would RS485
do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for
the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good
example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each
line
and at each end of the backplane (or you can use active termination).
VME
also defines the driver characteristics, and you can buy chips
specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3
row
DIN41612 type for standard VME16 and VME32).

Mark.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

The design I was thinking of is probably a backplane that has an on-
board controller. The controller would receive commands from a PC
through USB or serial. Each daughter board would be enabled one at a
time using relays. Perhaps using MOSFETs for turning on power and
relays for routing clock and data. Once a daughter board is enabled,
another on-daughter-board controller (instructed by the main-board
controller) would route the signals to each chip perhaps using analog
switches or another set of relays. I don't know if this is too much
from a signal integrity standpoint.

The serial bandwidth is somewhere from 5 MHz to 20 MHz, i.e. each
serial clock would take from 50 ns to 200ns. The faster the better but
we could make it slower if signal integrity problems are unsolvable at
the high speed.

Does that sound reasonable? I'm also not sure how we would go about
characterizing capacitances, impedances, and such.

I agree with Mark: use VME or some other standard
bus/cardcage/connector convention. You can redefine the logic
protocols and power voltages if you want, but you'd be starting with a
structure that works.

Power mosfets on each board sounds sensible.

John

"John Larkin" <jjlarkin_at_highNOTlandTHIStechnologyPART.com> wrote in
message news:llm666hf1tscbe0l973950acpnm3bra5jd_at_4ax.com...
On Wed, 11 Aug 2010 17:30:07 -0700 (PDT), "M. Hamed"
mhelshou_at_hotmail.com> wrote:

On Aug 11, 5:03 pm, "markp" <map.nos...@f2s.com> wrote:
Is it a parallel bus or serial? What bandwidth do you need? Would RS485
do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for
the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good
example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each
line
and at each end of the backplane (or you can use active termination).
VME
also defines the driver characteristics, and you can buy chips
specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3
row
DIN41612 type for standard VME16 and VME32).

Mark.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

The design I was thinking of is probably a backplane that has an on-
board controller. The controller would receive commands from a PC
through USB or serial. Each daughter board would be enabled one at a
time using relays. Perhaps using MOSFETs for turning on power and
relays for routing clock and data. Once a daughter board is enabled,
another on-daughter-board controller (instructed by the main-board
controller) would route the signals to each chip perhaps using analog
switches or another set of relays. I don't know if this is too much
from a signal integrity standpoint.

The serial bandwidth is somewhere from 5 MHz to 20 MHz, i.e. each
serial clock would take from 50 ns to 200ns. The faster the better but
we could make it slower if signal integrity problems are unsolvable at
the high speed.

Does that sound reasonable? I'm also not sure how we would go about
characterizing capacitances, impedances, and such.

I agree with Mark: use VME or some other standard
bus/cardcage/connector convention. You can redefine the logic
protocols and power voltages if you want, but you'd be starting with a
structure that works.

Power mosfets on each board sounds sensible.

John


One caveat, if you use a VME backplane (or any parallel backplane) you
should use it as a parallel bus only and use the same strobe signals, data
signals and address signals as VME does. The backplane may not have
particularly good crosstalk figures between data or address lines (as they
ususally are all generated at once and strobed once stable), so it's not a
good idea to send individual clocks on them.

You could use a custom backplane with RS485 (i.e. differential serial) and
power, your speeds are in the right ballpark for that. In this case you
could have RS485 receivers on a card that grabs the packet, determines
whether it was addressed, powers up the relevant logic on the card, passes
the serial stuff on to the local device, then sends the reply back down
the backplane.

Mark.

On Aug 11, 4:17 pm, linnix <m...@linnix.info-for.us> wrote:

Q#1: How many daughters?

We're thinking perhaps 10-15 boards at a time.

Q#2: Are you sure they can't be serially communicated.

Could you please elaborate?

What would the topology be?

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

"markp" <map.nospam_at_f2s.com> wrote in message
news:8chuj7Fpm6U1_at_mid.individual.net...

"John Larkin" <jjlarkin_at_highNOTlandTHIStechnologyPART.com> wrote in
message news:llm666hf1tscbe0l973950acpnm3bra5jd_at_4ax.com...
On Wed, 11 Aug 2010 17:30:07 -0700 (PDT), "M. Hamed"
mhelshou_at_hotmail.com> wrote:

On Aug 11, 5:03 pm, "markp" <map.nos...@f2s.com> wrote:
Is it a parallel bus or serial? What bandwidth do you need? Would RS485
do
the job?

Stacking is going to cause a lot of signal integrity issues, I'd go for
the
backplane (like in a 3U or 6U rack)

If you are thinking parallel bus, the VMEbus backplane is a good
example.
Basically you need to control the impedance of the backplane PCB. VME
backplanes are quite thick, and need termination resistor pairs on each
line
and at each end of the backplane (or you can use active termination).
VME
also defines the driver characteristics, and you can buy chips
specifically
for VME. There should only be one load on each signal, and the drivers
mounted close to the connectors to minimise stub lengths (which are 3
row
DIN41612 type for standard VME16 and VME32).

Mark.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

The design I was thinking of is probably a backplane that has an on-
board controller. The controller would receive commands from a PC
through USB or serial. Each daughter board would be enabled one at a
time using relays. Perhaps using MOSFETs for turning on power and
relays for routing clock and data. Once a daughter board is enabled,
another on-daughter-board controller (instructed by the main-board
controller) would route the signals to each chip perhaps using analog
switches or another set of relays. I don't know if this is too much
from a signal integrity standpoint.

The serial bandwidth is somewhere from 5 MHz to 20 MHz, i.e. each
serial clock would take from 50 ns to 200ns. The faster the better but
we could make it slower if signal integrity problems are unsolvable at
the high speed.

Does that sound reasonable? I'm also not sure how we would go about
characterizing capacitances, impedances, and such.

I agree with Mark: use VME or some other standard
bus/cardcage/connector convention. You can redefine the logic
protocols and power voltages if you want, but you'd be starting with a
structure that works.

Power mosfets on each board sounds sensible.

John


One caveat, if you use a VME backplane (or any parallel backplane) you
should use it as a parallel bus only and use the same strobe signals, data
signals and address signals as VME does. The backplane may not have
particularly good crosstalk figures between data or address lines (as they
ususally are all generated at once and strobed once stable), so it's not a
good idea to send individual clocks on them.

You could use a custom backplane with RS485 (i.e. differential serial) and
power, your speeds are in the right ballpark for that. In this case you
could have RS485 receivers on a card that grabs the packet, determines
whether it was addressed, powers up the relevant logic on the card, passes
the serial stuff on to the local device, then sends the reply back down
the backplane.

Mark.

Having said that, it seems your serial interface is synchronous. The RS485
approach assumes asynchronous data (with a fast UART for reception and
transmission on the cards and the controller). One problem you are going to
face is skew between the clock and data in any synchronous system on the
backplane, unless you Manchester encode or somehow embed the clock, but that
will reduce your bandwidth.

Mark.

Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.

None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.

We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.

Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.

Help is appreciated! Thanks.

Hello there,

I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.

None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.

We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.

Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.

It's a serial bus (CLK+DATA) plus some other control signals that are
relatively constant. Communication is bidirectional. would the VME bus
be still relevant in this case?

If I had to design something that was guaranteed to work I'd have a 'master'
FPGA driving point to point LVDS/RS485 to each plug in position.

I'd use discrete transceivers for each channel for robustness (instead of
FPGA driven lvds).

The 'master' FPGA can then receive commands from the main controller and
do the multiplexing of messages to and from each plug in card.'