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JosephKK
Guest
Thu Aug 19, 2010 11:17 am
On Wed, 11 Aug 2010 16:02:26 -0700 (PDT), "M. Hamed"
<mhelshou_at_hotmail.com> wrote:
Quote:
Hello there,
I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.
None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.
We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.
Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.
Help is appreciated! Thanks.
If you want fast signals try controller per duaghterboard ala PCIe
serial channels.
JosephKK
Guest
Thu Aug 19, 2010 12:13 pm
On Thu, 12 Aug 2010 10:18:55 -0700 (PDT), "M. Hamed"
<mhelshou_at_hotmail.com> wrote:
Quote:
Thanks all for chipping in.
to answer a few questions:
1) Yes the protocol is SPI-like.
2) To clarify, This will function more as a test equipment with the
chips to be tested on the daughter board. It's not something that will
be marketed
but it's still in the phase of determining feasibility, and whether we
can design it in-house or we'd have to bring outside experience.
3) We would expect the backplane to last for years but it can be
revised or replaced when necessary. The daughter boards should be
easily replaced.
4) The protocol of communication is already defined by the chips on
the daughter boards so we don't have much leverage here.
5) As I mentioned before the bandwidth is somewhere from 5 MHz to 20
MHz
I also have some questions unanswered:
1) Would the VME bus be an overkill for this? is there a similar
standard for Synchronous Serial busses that I can get via off-the-
shelf boards?
2) I don't know if the USB to SPI would be applicable here since the
SPI protocol is bidirectional and I thought USB is polled only. We
also would like to mimic as much as possible the setup in which these
daughter boards will be deployed. I also kind of feel that USB would
be more complicated to deal with
3) The FPGA idea sounds interesting but I'd like the lines to be
bidirectional and would like to be able to vary the voltage for
reliability testing over
multiple voltages.
From all the responses it seems to me that this project may be more
involved than what we initially thought and may go beyond our skills.
But we were hoping that it would be a learning experience and
something we'd add to our arsenal. But if it turns out to be
infeasible we'd have to outsource help.
It sounds like it is just a bit beyond your proven skills, but is it
beyond your economical (and timely) learning rate? Yeah, i could come
here to resolve that kind of question myself. I suspect that with
help it is within your learning rate, usually a better solution for
the organization in the long term.
JosephKK
Guest
Fri Aug 20, 2010 12:18 am
On Thu, 12 Aug 2010 10:54:45 -0700 (PDT), linnix
<me_at_linnix.info-for.us> wrote:
Quote:
2) I don't know if the USB to SPI would be applicable here since the
SPI protocol is bidirectional and I thought USB is polled only.
Why?
USB to ethernet adapter can go in both directions, with synchronous
100Mbits on the ethernet side.
I do not understand how you are applying synchronous to 100BASE-TX.
Where in 802.3 does one find it?
lynchaj
Guest
Thu Sep 02, 2010 2:31 am
On Aug 11, 7:02 pm, "M. Hamed" <mhels...@hotmail.com> wrote:
Quote:
Hello there,
I'm part of a team that has been assigned the task of designing a
system consisting of a backplane and a number of daughter board. Each
daughter board will have a large number of chips. The main board will
need to communicate with one chip at a time but the communication
lines will go to every single chip and it's up to a controller
(possibly on the daughter board) to enable each chip individually.
None of us has enough experience with stacks of boards or backplanes.
We are worried that connecting one signal line to that many boards and
chips will introduce too many signal integrity problems and
capacitance that will make it impossible.
We are not sure whether the best topology would be a backplane and a
bunch of daughter boards connected via edge connectors or a stack of
boards with each board plugging into the board below it and the bottom
daughter board connecting to the backplane/motherboard. We think that
the latter approach would be worse especially for the boards higher up
in the stack of boards.
Can someone provide some advice over how to go about designing this
and what could be possible solutions? Are there any established design
practices? Are there any technical terms we should be looking up or
certain resources we should be consulting? As I mentioned we don't
have enough experience with this kind of problem. Most of what we've
done was single board systems.
Help is appreciated! Thanks.
Hi! As noted in previous replies, what you are describing sounds a
lot like S-100 or PC/XT ISA bus. They are both obsolete parallel
busses that are fairly simple to design and use. In particular S-100
is nice to use for an application as you describe because it is simple
and the parts are cheap and easy to use. The S-100 form factor is
excellent for prototyping because the boards offer 5"x10" area with a
lot of PCB space to implement your circuit. There are free EDA
templates for both boards for KiCAD available on the internet.
Although most S-100 boards are made using discrete TTL chips there is
no limitation to use obsolete or modern CPUs, microcontrollers, CPLDs
or even FPGAs. Each board will generally have its own voltage
regulators so you can operate with almost any voltage level such as
5V, 3.3V, or less. There is a small but active community of S-100
home brew computing hobbyists still making S-100 boards and the tools
needed to make your own boards are either free or very inexpensive.
It really is an economical approach to making prototyping and it
sounds like it would fit your requirement well.
You can see for yourself at S100computers.com and/or the N8VEM home
brew computing project. Good luck with your project!
Thanks and have a nice day!
Andrew Lynch
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