Back Annotation simulations

Hi colleagues,

I have got a SDF file from another colleague. I need to do back-annotated
simulations on this design. Now I would like to know what tools and the
procedure should be followed for doing the back-annotation simulations.
This
is the first time for me to do back-annotated simulations.


Thanks in advance.
rajan

Hi,

I think you can do time analysis and power analysis in PrimeTime and
Power compiler of Synopsys respectively. Those tools can work on gate
level netlist, usually for architecture design.

In PrimeTime and power compiler, if you don't use SDF file, you can
define a wireload model to estimate the wire parasistics and
resistance. Anyway, the model is not accurate, since it doesn't
consider placement&route. So you need back-annotation.

I think SDF file only talk about the wires (P&R) but gates. Gates
information can be extracted from Synopsys library.

If you already extracted transistor level netlist from layout. You can
run Hspice, Spetre or NanoSim (much faster) for the simulation. In
this case, the back-annotation is not neccessary.

If I am not right, correct me please.


"rajan" <rajan100000_at_hotmail.com> wrote in message
news:<cf2f8d$8la$1_at_reader08.wxs.nl>...
Hi colleagues,

I have got a SDF file from another colleague. I need to do
back-annotated
simulations on this design. Now I would like to know what tools and the
procedure should be followed for doing the back-annotation simulations.
This
is the first time for me to do back-annotated simulations.


Thanks in advance.
rajan