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Automatic Schematic Generation (System Graph) and Viewer

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elektroda.net NewsGroups Forum Index - Synthesis - Automatic Schematic Generation (System Graph) and Viewer

Alfonso Acosta
Guest

Thu Jul 19, 2007 5:17 am   



Hi all,

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Does any one know about a specific, open file format for schematics?
My best options so far are GXL (http://www.gupro.de/GXL/) and GraphML
(http://graphml.graphdrawing.org/) but I coudn't find any free viewer
with automatic routing support.

Any help would be appreciated. Thanks in advance,

Alfonso Acosta

Clunixchit
Guest

Mon Jul 23, 2007 12:32 pm   



On Jul 19, 6:17 am, Alfonso Acosta <alfonso.aco...@gmail.com> wrote:
Quote:
To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Try the Alliance VLSI CAD, it is free and open source.

http://www-asim.lip6.fr/recherche/alliance/

One of its tools, boog can take a HDL model and generates a schematic
which can be read with its xsch schematic viewer.

PS: try it under a redhat or fedora based distribution or its clones.
On a debian based distro, I had problems in installing alliance to be
used with other commercial products.

Chitlesh

krw
Guest

Mon Jul 23, 2007 2:06 pm   



In article <1184818661.311313.125080_at_x35g2000prf.googlegroups.com>,
alfonso.acosta_at_gmail.com says...
Quote:
Hi all,

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe: http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Synplify Pro does (with HDL Analyst). It also generates bubble
charts (something you might think about doing also).

<snip>

--
Keith

Shannon
Guest

Mon Jul 23, 2007 3:59 pm   



On Jul 23, 6:06 am, krw <k...@att.bizzzz> wrote:
Quote:
In article <1184818661.311313.125...@x35g2000prf.googlegroups.com>,
alfonso.aco...@gmail.com says...

Hi all,

I'm developing a System Description Language (which could be used as
an HDL in particular) called ForSyDe:http://www.ict.kth.se/info/FOFU/ForSyDe/

I'm planning to add a backend to my compiler wich generates a
graphical representation of the system.

To my surprise, I havent found any tool which generates a schematic or
system graph given a HDL model. Does anyone know any of them?

Synplify Pro does (with HDL Analyst). It also generates bubble
charts (something you might think about doing also).

snip

--
Keith

Quartus II also has an RTL view and state-machine bubble viewer.
ModelSim does as well. In fact, do any of the major tools NOT have a
schematic viewer?

Shannon

elektroda.net NewsGroups Forum Index - Synthesis - Automatic Schematic Generation (System Graph) and Viewer

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