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Asynchronous FIFO

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qq
Guest

Fri Feb 09, 2018 6:12 am   



For https://i.imgur.com/3ZNs7KU.png and https://i.imgur.com/0ZEDmgS.png , why "If the synchronized read pointer’s MSB is high, the second MSB of the synchronized read pointer (rd_ptr_sync) is inverted before doing a comparison against a (n − 1) bit write pointer." ?

qq
Guest

Fri Feb 09, 2018 6:51 am   



It seems to me that the second MSB inversion is for solving the wrong FULL assertion in the case of rd_ptr=7 and wr_ptr=8

However, what about rd_ptr=7 and wr_ptr=6 instead ? This also does not generate the correct FULL signal ?

Richard Damon
Guest

Sat Feb 10, 2018 12:47 am   



On 2/8/18 11:12 PM, qq wrote:
Quote:
For https://i.imgur.com/3ZNs7KU.png and https://i.imgur.com/0ZEDmgS.png , why "If the synchronized read pointer’s MSB is high, the second MSB of the synchronized read pointer (rd_ptr_sync) is inverted before doing a comparison against a (n − 1) bit write pointer." ?


Note, the FIFO is 8 elements long, so is addressed with only 3 address
bits, but you have a 4 bit counter, so that MSB isn't part of the basic
comparison, but is being used to distinguish full from empty.

The counters are also Gray Counters.

If you look at the first page, if the write pointer is 8 locations above
the read pointer, then the bottom bits match, and the top two bits are
exactly opposite. By xoring the top most bit into the next to top most
when checking for full allows them to check only the bottom 3 (n-1) bits.

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