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Thomas Heller
Guest
Guest
Sun Jan 30, 2011 7:25 pm
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
entity spislave is
Port ( sysclock : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_strobe : out STD_LOGIC;
sclk : in STD_LOGIC;
mosi : in STD_LOGIC;
cs : in STD_LOGIC);
end spislave;
Then a typical instantiation is:
U1: spislave PORT MAP(
sysclock => clk64,
data_out => spi_data,
data_strobe => spi_strobe,
sclk => spi_clk,
mosi => spi_mosi,
cs => spi_cs
);
If I want to connect the data_out signal to parts of a databus then
I cannot write
data_out => data_bus(7 downto 0),
although I can write
sclk => not pin_7;
Can someone point me to a reference that explains which kind of 'things'
I can use in the instantiation?
Thanks,
Thomas
Jonathan Bromley
Guest
Guest
Sun Jan 30, 2011 10:09 pm
On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:
Quote:
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
entity spislave is
Port ( sysclock : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_strobe : out STD_LOGIC;
sclk : in STD_LOGIC;
mosi : in STD_LOGIC;
cs : in STD_LOGIC);
end spislave;
Then a typical instantiation is:
U1: spislave PORT MAP(
sysclock => clk64,
data_out => spi_data,
data_strobe => spi_strobe,
sclk => spi_clk,
mosi => spi_mosi,
cs => spi_cs
);
If I want to connect the data_out signal to parts of a databus then
I cannot write
data_out => data_bus(7 downto 0),
component instantiation. Say, I have a component declaration like this:
entity spislave is
Port ( sysclock : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_strobe : out STD_LOGIC;
sclk : in STD_LOGIC;
mosi : in STD_LOGIC;
cs : in STD_LOGIC);
end spislave;
Then a typical instantiation is:
U1: spislave PORT MAP(
sysclock => clk64,
data_out => spi_data,
data_strobe => spi_strobe,
sclk => spi_clk,
mosi => spi_mosi,
cs => spi_cs
);
If I want to connect the data_out signal to parts of a databus then
I cannot write
data_out => data_bus(7 downto 0),
Why not? Works for me. Who's complaining? Did you *really*
say (7 downto 0), or was there something non-static going on
in your slice range?
Quote:
although I can write
sclk => not pin_7;
sclk => not pin_7;
That's slightly different; the actual association can be
any monadic function of a signal. This was done to allow
for type conversions in the port map, but it works for
any monadic function and the "not" operator is, of course,
nothing more than the monadic function
function "not"(v: in std_logic) return std_logic;
Quote:
Can someone point me to a reference that explains which kind of 'things'
I can use in the instantiation?
I can use in the instantiation?
For an input port:
signals or slices thereof; expressions yielding a constant value.
For an output or inout port:
signals or slices thereof.
Conversion functions can be applied: they must be monadic,
and the syntax is different for input and output ports:
port map (some_input => F1(in_sig),
F2(some_output) => out_sig,
F3out(some_inout) => F3in(io_sig))
The actual must be a "static name" but that should be OK...
In VHDL-2008 you can put arbitrary expressions to an input port,
but your port will suffer an added delta cycle delay from the
implied process that computes the expression.
--
Jonathan Bromley
Thomas Heller
Guest
Guest
Thu Feb 03, 2011 9:49 pm
Am 30.01.2011 22:09, schrieb Jonathan Bromley:
Quote:
On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
entity spislave is
Port ( sysclock : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_strobe : out STD_LOGIC;
sclk : in STD_LOGIC;
mosi : in STD_LOGIC;
cs : in STD_LOGIC);
end spislave;
Then a typical instantiation is:
U1: spislave PORT MAP(
sysclock => clk64,
data_out => spi_data,
data_strobe => spi_strobe,
sclk => spi_clk,
mosi => spi_mosi,
cs => spi_cs
);
If I want to connect the data_out signal to parts of a databus then
I cannot write
data_out => data_bus(7 downto 0),
Why not? Works for me. Who's complaining? Did you *really*
say (7 downto 0), or was there something non-static going on
in your slice range?
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
entity spislave is
Port ( sysclock : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_strobe : out STD_LOGIC;
sclk : in STD_LOGIC;
mosi : in STD_LOGIC;
cs : in STD_LOGIC);
end spislave;
Then a typical instantiation is:
U1: spislave PORT MAP(
sysclock => clk64,
data_out => spi_data,
data_strobe => spi_strobe,
sclk => spi_clk,
mosi => spi_mosi,
cs => spi_cs
);
If I want to connect the data_out signal to parts of a databus then
I cannot write
data_out => data_bus(7 downto 0),
Why not? Works for me. Who's complaining? Did you *really*
say (7 downto 0), or was there something non-static going on
in your slice range?
I was confused. Of course it works.
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0) & "00000000",
...)
Is it possible to implement this without using another signal, like this:
adc_datainput <= data_bus(7 downto 0) & "00000000";
X: myinstance PORT MAP(
...
data_input => adc_input,
...)
Quote:
although I can write
sclk => not pin_7;
That's slightly different; the actual association can be
any monadic function of a signal. This was done to allow
for type conversions in the port map, but it works for
any monadic function and the "not" operator is, of course,
nothing more than the monadic function
function "not"(v: in std_logic) return std_logic;
Can someone point me to a reference that explains which kind of 'things'
I can use in the instantiation?
For an input port:
signals or slices thereof; expressions yielding a constant value.
For an output or inout port:
signals or slices thereof.
Conversion functions can be applied: they must be monadic,
and the syntax is different for input and output ports:
port map (some_input => F1(in_sig),
F2(some_output) => out_sig,
F3out(some_inout) => F3in(io_sig))
The actual must be a "static name" but that should be OK...
In VHDL-2008 you can put arbitrary expressions to an input port,
but your port will suffer an added delta cycle delay from the
implied process that computes the expression.
sclk => not pin_7;
That's slightly different; the actual association can be
any monadic function of a signal. This was done to allow
for type conversions in the port map, but it works for
any monadic function and the "not" operator is, of course,
nothing more than the monadic function
function "not"(v: in std_logic) return std_logic;
Can someone point me to a reference that explains which kind of 'things'
I can use in the instantiation?
For an input port:
signals or slices thereof; expressions yielding a constant value.
For an output or inout port:
signals or slices thereof.
Conversion functions can be applied: they must be monadic,
and the syntax is different for input and output ports:
port map (some_input => F1(in_sig),
F2(some_output) => out_sig,
F3out(some_inout) => F3in(io_sig))
The actual must be a "static name" but that should be OK...
In VHDL-2008 you can put arbitrary expressions to an input port,
but your port will suffer an added delta cycle delay from the
implied process that computes the expression.
Thanks for this useful info,
Thomas
Jonathan Bromley
Guest
Guest
Thu Feb 03, 2011 10:38 pm
On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote:
Quote:
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0) & "00000000",
...)
Is it possible to implement this without using another signal
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0) & "00000000",
...)
Is it possible to implement this without using another signal
Only in VHDL-2008, as far as I'm aware.
Have you tried
data_input(15 downto
=> data_bus(7 downto 0),
data_input(7 downto 0) => "00000000"
??? I know you can do that to split a vector port out to
several different signals, but I'm not sure whether it's
legal to mix constants and signals in that way.
--
Jonathan Bromley
Thomas Heller
Guest
Guest
Fri Feb 04, 2011 1:49 pm
Am 03.02.2011 22:38, schrieb Jonathan Bromley:
Quote:
On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller wrote:
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0)& "00000000",
...)
Is it possible to implement this without using another signal
Only in VHDL-2008, as far as I'm aware.
Have you tried
data_input(15 downto => data_bus(7 downto 0),
data_input(7 downto 0) => "00000000"
??? I know you can do that to split a vector port out to
several different signals, but I'm not sure whether it's
legal to mix constants and signals in that way.
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0)& "00000000",
...)
Is it possible to implement this without using another signal
Only in VHDL-2008, as far as I'm aware.
Have you tried
data_input(15 downto
=> data_bus(7 downto 0),
data_input(7 downto 0) => "00000000"
??? I know you can do that to split a vector port out to
several different signals, but I'm not sure whether it's
legal to mix constants and signals in that way.
Seems to work. Cool!
Thanks,
Thomas
rickman
Guest
Guest
Fri Feb 04, 2011 6:25 pm
On Jan 30, 4:09 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
Quote:
That's slightly different; the actual association can be
any monadic function of a signal.
Why did you use the term "monadic" rather than "unary"? Do I
misunderstand the meaning of either or both? It took me five minutes
to find a simple definition of "monadic function". That may sound
like a pretty short time, but when was the last time you spent five
minutes looking for a word definition? "Unary" is a much more common
term and I think more clear in this context unless there is some
useful connotation to "monadic" I don't appreciate.
Rick
Jonathan Bromley
Guest
Guest
Fri Feb 04, 2011 8:24 pm
On Fri, 4 Feb 2011 08:25:11 -0800 (PST), rickman wrote:
Quote:
Why did you use the term "monadic" rather than "unary"?
Thanks - that's a bit of jargon that I must have
incorrectly absorbed from somewhere. Now you've
provoked me into looking, I see that it's not even
strictly correct, at least not if you're a
mathematician or a (Haskell-style) functional
programmer. As you may guess, I am neither.
(Side note: some programming languages do tend to
use "monadic" and "dyadic" (and even "variadic")
to describe the number of arguments of a function.
APL is certainly one such. Maybe they're wrong too.)
Quote:
"Unary" is a much more common term
And rigorously accurate too. The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
Ho hum. Still getting things wrong after all
these years
--
Jonathan Bromley
rickman
Guest
Guest
Sat Feb 05, 2011 2:51 am
On Feb 4, 2:24 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
Quote:
On Fri, 4 Feb 2011 08:25:11 -0800 (PST), rickman wrote:
Why did you use the term "monadic" rather than "unary"?
Thanks - that's a bit of jargon that I must have
incorrectly absorbed from somewhere. Now you've
provoked me into looking, I see that it's not even
strictly correct, at least not if you're a
mathematician or a (Haskell-style) functional
programmer. As you may guess, I am neither.
(Side note: some programming languages do tend to
use "monadic" and "dyadic" (and even "variadic")
to describe the number of arguments of a function.
APL is certainly one such. Maybe they're wrong too.)
"Unary" is a much more common term
And rigorously accurate too. The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
Ho hum. Still getting things wrong after all
these years
Why did you use the term "monadic" rather than "unary"?
Thanks - that's a bit of jargon that I must have
incorrectly absorbed from somewhere. Now you've
provoked me into looking, I see that it's not even
strictly correct, at least not if you're a
mathematician or a (Haskell-style) functional
programmer. As you may guess, I am neither.
(Side note: some programming languages do tend to
use "monadic" and "dyadic" (and even "variadic")
to describe the number of arguments of a function.
APL is certainly one such. Maybe they're wrong too.)
"Unary" is a much more common term
And rigorously accurate too. The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
Ho hum. Still getting things wrong after all
these years
I didn't think much of it until I googled "monacdic" and found all
sorts of incomprehensible info (at least to me) that only remotely
seemed to apply to the context. Not being sure what monadic meant I
had to search for awhile until I found one definition which said, "1.
<programming> unary, when describing an operator or function."
I was adding my bias when I said unary is more common. But it seems
that monadic is equally correct, but there seems to be some
specialized usage in programming languages that was the part I found
incomprehensible.
Rick
Dave Higton
Guest
Guest
Sat Feb 05, 2011 8:32 pm
In message
<83b50900-e1e5-4983-9b82-a7b5c5bfee49_at_k16g2000vbq.googlegroups.com>
rickman <gnuarm_at_gmail.com> wrote:
Quote:
I didn't think much of it until I googled "monacdic" and found all
sorts of incomprehensible info (at least to me) that only remotely
seemed to apply to the context. Not being sure what monadic meant I
had to search for awhile until I found one definition which said, "1.
programming> unary, when describing an operator or function."
I was adding my bias when I said unary is more common. But it seems
that monadic is equally correct, but there seems to be some
specialized usage in programming languages that was the part I found
incomprehensible.
sorts of incomprehensible info (at least to me) that only remotely
seemed to apply to the context. Not being sure what monadic meant I
had to search for awhile until I found one definition which said, "1.
programming> unary, when describing an operator or function."
I was adding my bias when I said unary is more common. But it seems
that monadic is equally correct, but there seems to be some
specialized usage in programming languages that was the part I found
incomprehensible.
I remember reading the words "monadic" and "dyadic" for the first
time in the Motorola 6809 Preliminary Programmer's Reference
Manual.
Gosh, that's a long time ago.
Dave
Andy
Guest
Guest
Mon Feb 07, 2011 8:29 pm
On Feb 4, 1:24 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:
Quote:
The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
I agree, unary more commonly applies to operators with only one
operand. While all operators are functions (in vhdl), not all
functions are operators, and perhaps that would be a/the problem.
Would "unary function" imply a function that was invoked as a unary
operator?
What what would be the term for a function with zero arguments?
Nonadic? ;^)
OK, I did not look up monadic, but I took a lucky guess... and I knew
what dyadic meant, which helped a lot.
Andy
rickman
Guest
Guest
Tue Feb 08, 2011 5:39 am
On Feb 7, 1:29 pm, Andy <jonesa...@comcast.net> wrote:
Quote:
On Feb 4, 1:24 pm, Jonathan Bromley <s...@oxfordbromley.plus.com
wrote:
The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
I agree, unary more commonly applies to operators with only one
operand. While all operators are functions (in vhdl), not all
functions are operators, and perhaps that would be a/the problem.
Would "unary function" imply a function that was invoked as a unary
operator?
What what would be the term for a function with zero arguments?
Nonadic? ;^)
OK, I did not look up monadic, but I took a lucky guess... and I knew
what dyadic meant, which helped a lot.
Andy
wrote:
The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
I agree, unary more commonly applies to operators with only one
operand. While all operators are functions (in vhdl), not all
functions are operators, and perhaps that would be a/the problem.
Would "unary function" imply a function that was invoked as a unary
operator?
What what would be the term for a function with zero arguments?
Nonadic? ;^)
OK, I did not look up monadic, but I took a lucky guess... and I knew
what dyadic meant, which helped a lot.
Andy
Maybe you should have looked up Nonadic...
nonadic (comparative more nonadic, superlative most nonadic)
1. of or pertaining to an nonad; ninefold
Rick
rickman
Guest
Guest
Tue Feb 08, 2011 5:40 am
On Feb 7, 1:29 pm, Andy <jonesa...@comcast.net> wrote:
Quote:
On Feb 4, 1:24 pm, Jonathan Bromley <s...@oxfordbromley.plus.com
wrote:
The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
I agree, unary more commonly applies to operators with only one
operand. While all operators are functions (in vhdl), not all
functions are operators, and perhaps that would be a/the problem.
Would "unary function" imply a function that was invoked as a unary
operator?
What what would be the term for a function with zero arguments?
Nonadic? ;^)
OK, I did not look up monadic, but I took a lucky guess... and I knew
what dyadic meant, which helped a lot.
Andy
wrote:
The style-checker
in my head (which usually serves me tolerably well)
has no problem with "unary operator", but finds
the sound of "unary function" rather strange.
Time for a re-calibrate, maybe.
I agree, unary more commonly applies to operators with only one
operand. While all operators are functions (in vhdl), not all
functions are operators, and perhaps that would be a/the problem.
Would "unary function" imply a function that was invoked as a unary
operator?
What what would be the term for a function with zero arguments?
Nonadic? ;^)
OK, I did not look up monadic, but I took a lucky guess... and I knew
what dyadic meant, which helped a lot.
Andy
Or maybe you should have looked up "unary function"?
Rick
Brian Drummond
Guest
Guest
Wed Feb 09, 2011 2:55 pm
On Thu, 03 Feb 2011 21:49:58 +0100, Thomas Heller <theller_at_ctypes.org> wrote:
Quote:
Am 30.01.2011 22:09, schrieb Jonathan Bromley:
On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0) & "00000000",
...)
the actual association can be
any monadic function of a signal. This was done to allow
for type conversions in the port map, but it works for
any monadic function
On Sun, 30 Jan 2011 19:25:38 +0100, Thomas Heller wrote:
I do not understand what I can use in the association list of a
component instantiation. Say, I have a component declaration like this:
What I really want and what didn't work is connecting some bits of an
input signal on the component (say, the data bus of an ADC) to a signal,
and other bits to a constant. Example:
X: myinstance PORT MAP(
...
data_input => data_bus(7 downto 0) & "00000000",
...)
the actual association can be
any monadic function of a signal. This was done to allow
for type conversions in the port map, but it works for
any monadic function
then
data_input => pad_low_byte(data_bus(7 downto 0)),
ought to work, yes?
Writing the function pad_low_byte should be a simple exercise.
One caveat : some design tools (including older Xilinx synthesis tools) place
unnecessary restrictions on what you can do in port associations, either
explicitly, or by triggering tool bugs.
- Brian
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