ASIC RTL and FPGA RTL

Mon Apr 26, 2004 5:10 am   

Hi,

I was talking to an "expert" in synthesis and he mentioned that there is
a lot of difference between a synthesizable RTL code for a FPGA and a
synthesizable RTL code for an ASIC.

Is this true?

If so, could you please point the significant differences between the
two and what causes these differences.

Thanks,
Anand

Mon Apr 26, 2004 12:09 pm   

Anand P Paralkar <anandp_at_sasken.nospam.com> wrote in message news:<408CA510.58B2962C_at_sasken.nospam.com>...

You may be interested to read the recent article from eedesign.com:

http://www.eedesign.com/features/exclusive/showArticle.jhtml?articleId=18901725&kc=4235

Regards,
Alexander Gnusin