EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

Array pipeline

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - VHDL Language - Array pipeline

hssig
Guest

Fri Apr 01, 2011 8:50 am   



Hi,

I want to declare an array "vecarr " which consists of
std_logic_vector, and a second
array "arr3d " to pipeline the first array.
When simuating the following test code Modelsim complains:
** Fatal: (vsim-3734) Index value 0 is out of range 4 downto 1.


------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity arr_pipe is
end entity;

architecture xy of arr_pipe is

type t_vecarr is array(natural range <>) of std_logic_vector(7 downto
0);
signal vecarr : t_vecarr(15 downto 0) := (others => (others => '1'));
type t_arr3d is array(natural range <>) of t_vecarr(15 downto 0);
signal arr3d : t_arr3d(4 downto 0);
signal clk : std_logic;

begin

process
begin
clk <= '1'; wait for 5 ns;
clk <= '0'; wait for 5 ns;
end process;

process(clk)
begin
if rising_edge(clk) then
for m in 0 to 15 loop
arr3d(arr3d'high)(m) <= vecarr(m);
arr3d(arr3d'high-1 downto 0)(m) <= arr3d(arr3d'high
downto 1)(m); --** ERROR
end loop;
end if;
end process;

end xy;
------------------------------------------------------------------------------------------------


Can someone explain to me what is wrong about that shift register ?

Cheers,
hssig

Jonathan Bromley
Guest

Fri Apr 01, 2011 1:10 pm   



On Apr 1, 7:50 am, hssig wrote:

Quote:
arr3d(arr3d'high-1 downto 0)(m)
= arr3d(arr3d'high downto 1)(m);  --** ERROR

Huh? You're taking a slice of an array, and then
trying to subscript it? I didn't think that was
possible, but it seems that maybe it is (must go
check the LRM!) and the (m) is being used as a
subscript into the slice arr3d(arr3d'high-1 downto 0).

You need an inner for-loop to do that copy,
scanning over the first subscript of arr3d.

I don't see why you need the m-loop at all,
since you're just copying bits broadside.
What's wrong with this:

arr3d(arr3d'high) <= vecarr;
arr3d(arr3d'high-1 downto 0)
<= arr3d(arr3d'high downto 1);

Or something like this...

for i in arr3d'range loop
if i = arr3d'high then
arr3d(i) <= vecarr;
else
arr3d(i) <= arr3d(i+1);
end if;
end loop;

I don't see the need for a loop scanning over
the subcomponents of the t_vecarr objects.
--
Jonathan Bromley

hssig
Guest

Mon Apr 04, 2011 9:45 am   



Hi Jonathan,

thank you for your alternative description. I have just been curious
about the reason why my solution does
not work. Now it is clear.

Cheers,
hssig

elektroda.net NewsGroups Forum Index - VHDL Language - Array pipeline

Ask a question - edaboard.com

Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
RTV map EDAboard.com map News map EDAboard.eu map EDAboard.de map EDAboard.co.uk map Opony