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Array of std_logic_vector

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Guest

Tue Jan 28, 2020 4:45 pm   



type PACKET_REG_TYPE is array (0 to 127) of std_logic_vector(7 downto 0);

signal common_stream_header : std_logic_vector(63 downto 0);
signal stream_1_tx_int : PACKET_REG_TYPE;


stream_1_tx_int(3 to 10) <= common_stream_header; -- FAIL. Same number bits on each side??
Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR.
(vcom-1272) Length of expected is 8; length of actual is 64.

stream_1_tx_int(3 to 4) <= common_stream_header(63 downto 4Cool; -- FAIL.
Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR.
(vcom-1272) Length of expected is 2; length of slice name is 16.

stream_1_tx_int(3 to 4) <= PACKET_REG_TYPE(common_stream_header(63 downto 4Cool); -- FAIL.
(vcom-1583) Illegal type converson from 'ieee.std_logic_1164.STD_LOGIC_VECTOR' to 'dut_lib.spis_sclk_pkg.PACKET_REG_TYPE' (array element type difference).
(vcom-1272) Length of type "PACKET_REG_TYPE" is 1046; length of operand is 16.
(vcom-1272) Length of expected is 2; length of actual is 1046.

stream_1_tx_int(3 to 4) <= common_stream_header(63 downto 56) & common_stream_header(55 downto 4Cool; -- PASS.

I have an array of bytes as defined above. I want to make assignments to multiple array elements at a time but am having a lot of trouble. In the first example I try to assign a 64-bit signal to 8 elements of the array which ends up being 64-bits as well. It doesn’t work.

I can’t figure why none of the examples of array assignment work?? I even tried type casting. I finally got my code to compile with the last example but it makes coding cumbersome.

Is there a better way to do this. As a note, I tried the VHDL 2008 switch in Modelsim but it just started complaining about my (others => (others => ‘0’) assignments.

KJ
Guest

Tue Jan 28, 2020 6:45 pm   



On Tuesday, January 28, 2020 at 10:35:56 AM UTC-5, digita...@gmail.com >
> Is there a better way to do this. As a note, I tried the VHDL 2008 switch in Modelsim but it just started complaining about my (others => (others => ‘0’) assignments.

A better way to be to define PACKET_REG_TYPE a bit differently and then use it for common_stream_header like this:

type PACKET_REG_TYPE is array (natural range <>) of std_logic_vector(7 downto 0);
signal common_stream_header : PACKET_REG_TYPE(0 to 7);
signal stream_1_tx_int : PACKET_REG_TYPE(0 to 127);

Then you can assign like this:
stream_1_tx_int(3 to 10) <= common_stream_header;

Note a couple of things:
- The basic problem you have is thinking that a 64 entry array is equivalent to an 8x8 array, it's not.
- PACKET_REG_TYPE is now an unconstrained array. When you declare signals/variables of that type you need to supply the range as shown.
- The assignment of the particular 'bytes' of stream_1_tx_int is all done in one step.

Kevin Jennings

Rick C
Guest

Tue Jan 28, 2020 9:53 pm   



On Tuesday, January 28, 2020 at 10:35:56 AM UTC-5, digita...@gmail.com wrote:
Quote:
type PACKET_REG_TYPE is array (0 to 127) of std_logic_vector(7 downto 0);

signal common_stream_header : std_logic_vector(63 downto 0);
signal stream_1_tx_int : PACKET_REG_TYPE;


stream_1_tx_int(3 to 10) <= common_stream_header; -- FAIL. Same number bits on each side??
Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR.
(vcom-1272) Length of expected is 8; length of actual is 64.

stream_1_tx_int(3 to 4) <= common_stream_header(63 downto 4Cool; -- FAIL..
Target type dut_lib.spis_sclk_pkg.PACKET_REG_TYPE in signal assignment is different from expression type ieee.std_logic_1164.STD_LOGIC_VECTOR.
(vcom-1272) Length of expected is 2; length of slice name is 16.

stream_1_tx_int(3 to 4) <= PACKET_REG_TYPE(common_stream_header(63 downto 4Cool); -- FAIL.
(vcom-1583) Illegal type converson from 'ieee.std_logic_1164.STD_LOGIC_VECTOR' to 'dut_lib.spis_sclk_pkg.PACKET_REG_TYPE' (array element type difference).
(vcom-1272) Length of type "PACKET_REG_TYPE" is 1046; length of operand is 16.
(vcom-1272) Length of expected is 2; length of actual is 1046.

stream_1_tx_int(3 to 4) <= common_stream_header(63 downto 56) & common_stream_header(55 downto 4Cool; -- PASS.

I have an array of bytes as defined above. I want to make assignments to multiple array elements at a time but am having a lot of trouble. In the first example I try to assign a 64-bit signal to 8 elements of the array which ends up being 64-bits as well. It doesn’t work.

I can’t figure why none of the examples of array assignment work?? I even tried type casting. I finally got my code to compile with the last example but it makes coding cumbersome.


You could try defining a function that accepts as input the common_stream_header data type and returns the array slice you need. I assume you want to avoid the typing of four lines to do the assignment in multiple places. The function will encapsulate that.


> Is there a better way to do this. As a note, I tried the VHDL 2008 switch in Modelsim but it just started complaining about my (others => (others => ‘0’) assignments.

I would figure out what is going on with this. VHDL2008 doesn't break things that I know of.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209


Guest

Wed Jan 29, 2020 4:45 am   



Thank you for your reply. It is really helpful. From this I take it that since PACKET_REG_TYPE is specified as a byte then all assignments must be based on a byte.

I didn’t paste all of the code but there is another array of ADC data: type ADC_REG_TYPE is array (0 to 20) of std_logic_vector(31 downto 0). In order to assign this ADC data to my stream array I take it I would have to repackage it like: Signal adc_data : PACKET_REG_TYPE(0 to 83).

Then I could assign the whole thing at once:
stream_1_tx_int(11 to 94) <= adc_data;

Or

I could assign one channel as:
stream_1_tx_data(11 to 14) <= adc_data(0 to 3);

Thanks again for your help.

KJ
Guest

Wed Jan 29, 2020 1:56 pm   



On Tuesday, January 28, 2020 at 10:10:39 PM UTC-5, digita...@gmail.com wrote:

Quote:
I didn’t paste all of the code but there is another array of ADC data: type ADC_REG_TYPE is array (0 to 20) of std_logic_vector(31 downto 0). In order to assign this ADC data to my stream array I take it I would have to repackage it like: Signal adc_data : PACKET_REG_TYPE(0 to 83).

Then I could assign the whole thing at once:
stream_1_tx_int(11 to 94) <= adc_data;

Yes, but since ADC data is an array of 32 bit things, you would need to manually convert between 32 bit words and 8 bit ones. However, to do this conversion you could build on what you have.


type PACKET_REG_TYPE32 is array(natural range <>) of std_logic_vector(31 downto 0);

Then create a function that converts a 32 bit word into an array of four bytes. The declaration for this is shown below, you would write the body of the function.

function ToPacketRegType(Inp: std_logic_vector(31 downto 0)) return PACKET_REG_TYPE;

Then create a function that converts PACKET_REG_TYPE32 to PACKET_REG_TYPE by iterating and calling the function ToPacketRegType. Again, you would write the body of the function.

function ToPacketRegType(Inp: PACKET_REG_TYPE32) return PACKET_REG_TYPE;

Now that you have these to helper functions you can convert directly from your ADC data array like this

AdcDataPacketRegType <= ToPacketRegType(AdcData);

Alternatively, you would dispense with AdcDataPacketRegType and simply assign ToPacketRegType(AdcData) into the appropriate range in your packet.

Kevin Jennings

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