Are there any differences between 'Synplicity VHDL compiler,

Wed Oct 13, 2010 11:00 am   

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Hi,

Are there any differences between 'Synplicity VHDL compiler, v1.0,
b. 074R' and GHDL compiler?

Thanks.
- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

When making your choices in life, do not forget to live. (Samuel
Johnson)
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Thu Oct 14, 2010 8:13 am   

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backhus <goouse99_at_googlemail.com> writes:



- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --
- --

You cannot escape the responsibility of tomorrow by evading it
today. (Abraham Lincoln)
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Thu Oct 14, 2010 9:11 am   

On 13 Okt., 12:00, Merciadri Luca <Luca.Mercia...@student.ulg.ac.be>
wrote:

Hi,
Synplicity(now owned by Synopsys) tools (namely Synplify) are for
synthesis. They have a comercial license.
GHDL is an open source simulation tool.

Have a nice synthesis
Eilert

Thu Oct 14, 2010 2:29 pm   

On Oct 14, 8:13 am, Merciadri Luca <Luca.Mercia...@student.ulg.ac.be>
wrote:

They will certainly be different. Finding out what the specific
differences, limitations and bugs are may be near impossible though!

In theory the VHDL LRM (Language Reference Manual) provides sufficient
information for all compilers to behave identically (assuming they are
LRM compliant) regardless of the underlying implementation details.
Tool vendors will usually claim compliance to a particular version of
the standard with certain exceptions. AFAIK no tool vendors fully
support VHDL-2008 yet.

In practice, you will find that certain tools require work-arounds to
navigate deficiencies and bugs. The way the Xilinx tools handle
libraries and record types appears to be a poorly executed
afterthought, though the new parser improves matters slightly. All
tools have their own niggles and foibles to discover - not always a
fun experience.

Chris

Thu Oct 14, 2010 3:03 pm   

Perhaps take 30 minutes and read up about what the different tools
do. One hint: Synplify and GHDL perform completely different tasks.
The only common element is that the input is VHDL.

KJ

Thu Oct 14, 2010 9:40 pm   

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Thanks for both messages. I will take a deeper look into this when
I'll have spare time.

- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

When love and skill work together, expect a masterpiece. (John
Ruskin)
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