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any good systemverilog resources

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elektroda.net NewsGroups Forum Index - Verilog Language - any good systemverilog resources

alb
Guest

Sun Jan 08, 2017 9:48 pm   



Hi everyone,

I'm not sure whether there are many systemverilog folks hanging around here but
I'll give it a try.

I'm trying to ramp up a bit my systemverilog basics and I'd like to get some
good resources (books, slides, sites, etc.). I've been using SV for the past 4
months and even though I can easily follow through the code, I still feel very
clumsy.

Any pointer would be appreciated,

Al

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
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nemgreen@gmail.com
Guest

Mon Jan 09, 2017 12:39 pm   



On Sunday, 8 January 2017 14:48:59 UTC, alb wrote:
Quote:
Hi everyone,

I'm not sure whether there are many systemverilog folks hanging around here but
I'll give it a try.

I'm trying to ramp up a bit my systemverilog basics and I'd like to get some
good resources (books, slides, sites, etc.). I've been using SV for the past 4
months and even though I can easily follow through the code, I still feel very
clumsy.

Any pointer would be appreciated,

Al

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?


The IEEE LRM is available for anyone to download and is fairly readable relative to other LRMs
https://standards.ieee.org/getieee/1800/download/1800-2012.pdf

mag
Guest

Tue Jan 10, 2017 7:44 pm   



On 2017-01-08 14:48:56 +0000, alb said:

Quote:
Hi everyone,

I'm not sure whether there are many systemverilog folks hanging around here but
I'll give it a try.

I'm trying to ramp up a bit my systemverilog basics and I'd like to get some
good resources (books, slides, sites, etc.). I've been using SV for the past 4
months and even though I can easily follow through the code, I still feel very
clumsy.

Any pointer would be appreciated,

Al


Books:
http://a.co/fDkzf8i
http://a.co/56Us4BE

Class:
http://www.doulos.com/content/training/systemverilog_comprehensive.php

hope this helps

alb
Guest

Fri Jan 13, 2017 5:38 am   



Hi Mag,

mag <mag_at_nospam.com> wrote:
Quote:


This one I have indeed, haven't started reading it.

> http://a.co/56Us4BE

I'm not so interested in the design part. We are still using verilog for the
digital and pretty much schematics for the analog.

Quote:


I guess that from a language perspective I kind of understand all the
basic ideas (even though I find the typing somewhat odd). Maybe I'd like to have
something more concerning the verification methodology, when to use assertion,
programs vs modules, functions vs tasks, it seems a big collection of paradigms
but without a clear indication on how to use them.


Guest

Thu Feb 16, 2017 9:33 am   



I'd highly recommend "SystemVerilog for Design." Sutherland is a fantastic authority on Verilog design practices in general but this book covers everything. It's not all about design. The authors do include a lot of info about what is and isn't synthesizeable.

IMHO, if Verilog isn't synthesizable, there is zero point in my using or learning it. I'll use C/C++ or Python or whatever else I can get my hands on to do generic logic stuff. Non-synthesizable Verilog is great for testbenches, which are super important, but you still need to know what will and will not end up on a board.

Idk. The "design" side of Verilog is super popular for some reason. I'm not quite sure why. I can only live in theory land for so long before I feel like I'm wasting my life, lol.

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