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another OVL question

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elektroda.net NewsGroups Forum Index - Verilog Language - another OVL question

mag
Guest

Wed Nov 30, 2011 7:02 pm   



Is there every an instance where using OVL would be preferred over SVA?
Seems to me OVL is there for people who want to use assertions but
don't want to learn SVA, or who want to use assertions using some other
language than SV.

Thanks.


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Swapnajit
Guest

Sun Dec 18, 2011 9:46 am   



Yes, those instances will be:

- My legacy code uses OVL and I do not have time or resource to modify the code.
- I have not upgraded my free simulator that is still working on supporting v2k to a paid one that supports SVA.
- I use VHDL and SVA is of no use for me.

Tough management problems!
--
Project VeriPage:: http://www.project-veripage.com

elektroda.net NewsGroups Forum Index - Verilog Language - another OVL question

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