Another discrepancy (LTspice/switchcad3)

Mon May 30, 2005 7:58 pm   

The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:

Version 4
SHEET 1 1000 680
WIRE -400 352 -400 -96
WIRE -272 80 -272 32
WIRE -272 224 -272 160
WIRE -272 256 -272 224
WIRE -272 432 -272 336
WIRE -176 528 -176 304
WIRE -176 608 -176 592
WIRE -160 -96 -400 -96
WIRE -160 144 -160 -16
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WIRE -144 608 -176 608
WIRE -144 608 -144 480
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WIRE 592 384 592 336
WIRE 592 416 592 384
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SYMBOL nmos 544 240 R0
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SYMATTR Value IRF7343N
SYMBOL res 576 400 R0
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SYMATTR Value 0.22
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SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 480 -128 R0
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SYMATTR Value 100V
SYMBOL cap 880 288 R0
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SYMATTR InstName U1
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SYMBOL cap 656 208 R90
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SYMATTR Value 4700pF
SYMBOL cap 512 80 R0
WINDOW 0 -63 4 Left 0
WINDOW 3 -84 60 Left 0
SYMATTR InstName C5
SYMATTR Value 5.0µF
TEXT 528 224 Left 0 ;N009
TEXT -312 664 Left 0 !.tran 0 25uSEC 0uSec 0.001uSEC
TEXT 448 408 Left 0 ;N006
TEXT 376 344 Left 0 ;N007

Mon May 30, 2005 8:57 pm   

Robert,


The simulation is probably right around correct. That
FET and diode have capacitance. Below is a working 1619
circuit you might use as stating point.

--Mike

--- 1619.asc ---


Version 4
SHEET 1 2528 1112
WIRE 944 1040 944 800
WIRE 976 960 976 880
WIRE 976 992 976 960
WIRE 1008 544 1008 512
WIRE 1008 656 1008 624
WIRE 1008 880 976 880
WIRE 1056 960 976 960
WIRE 1088 880 1072 880
WIRE 1152 512 1008 512
WIRE 1152 720 1152 512
WIRE 1184 880 1168 880
WIRE 1184 960 1120 960
WIRE 1184 960 1184 880
WIRE 1216 720 1152 720
WIRE 1216 800 944 800
WIRE 1216 880 1184 880
WIRE 1376 512 1152 512
WIRE 1376 656 1376 512
WIRE 1376 992 1376 944
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WIRE 1696 512 1376 512
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WIRE 1696 880 1536 880
WIRE 1696 880 1696 816
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WIRE 1792 1040 944 1040
WIRE 1792 1040 1792 848
WIRE 1888 640 1584 640
WIRE 1888 704 1840 704
WIRE 1888 704 1888 640
WIRE 1888 736 1888 704
WIRE 1888 848 1792 848
WIRE 1888 848 1888 816
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WIRE 2016 976 2016 880
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SYMATTR InstName L1
SYMATTR Value 12µ
SYMBOL NMOS 1648 720 R0
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WINDOW 3 60 84 Left 0
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SYMATTR Value Si9804DY
SYMBOL VOLTAGE 1008 528 R0
SYMATTR InstName V1
SYMATTR Value 3.3
SYMBOL cap 1120 944 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C2
SYMATTR Value 150p
SYMBOL cap 1072 864 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C4
SYMATTR Value .015µ
SYMBOL RES 1680 880 R0
SYMATTR InstName R3
SYMATTR Value 0.014
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SYMATTR InstName R2
SYMATTR Value 12.4K
SYMBOL res 1872 720 R0
SYMATTR InstName R1
SYMATTR Value 37.4K
SYMBOL res 1184 864 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 25K
SYMBOL cap 1568 656 R0
SYMATTR InstName C7
SYMATTR Value .1µ
SYMBOL polcap 2000 816 R0
SYMATTR InstName C6
SYMATTR Value 440µ
SYMATTR SpiceLine Rser=0.065
SYMBOL POWERPRODUCTS\\LT1619 1376 800 R0
SYMATTR InstName U1
SYMBOL schottky 1776 720 R270
WINDOW 0 32 32 VTop 0
WINDOW 3 0 32 VBottom 0
SYMATTR InstName D1
SYMATTR Value MBR735
SYMBOL res 2112 784 R0
SYMATTR InstName R5
SYMATTR Value 3
TEXT 1840 1024 Left 0 !.tran 4m startup



"Robert Baer" <robertbaer_at_earthlink.net> wrote in message
news:d8Lme.3891$MI4.26_at_newsread2.news.pas.earthlink.net...

Mon May 30, 2005 9:51 pm   

----- Original Message -----
From: "Robert Baer" <robertbaer_at_earthlink.net>
Newsgroups: sci.electronics.cad
Sent: Monday, May 30, 2005 10:58 PM
Subject: Another discrepancy (LTspice/switchcad3)



Hello Robert,

1.
You have to choose parts which stands the 5kV you have set
as target voltage. Your parts don't handle 5kV.

2. A ratio of 50 (Vout/100V) is a factor of 10 too high,
especially because the supply is already at 100V.

3. The capacitance of the components will limit the max.
possible voltage also.

I recommend to use at least a voltage multiplier and
eventually a transformer instead of the coil.


Best regards,
Helmut

Tue May 31, 2005 9:31 am   

Mike Engelhardt wrote:


------------ SNIPped for brevity ---------
Adding a small capacitance has no effect.
Even altering the ideal inductor to a resistive inductor with
parallel capacitance has no effect.
I will try your 1619 circuit later; i use a different OS for mail/NGs
than for "fancy" work (different drives also).

Tue May 31, 2005 9:35 am   

Helmut Sennewald wrote:


voltage; to see what SPICE would do.

**2. The real circuit will output about 1000V with a 4V inductor supply;
i do not think this is relevant.

**3. For real parts, that is part of what happens. I tried making the
inductor more complex by adding a small series resistor and then
paralling that combo with a small capacitor. That modification made
absolutely zero difference.

**"4". If i take my P17/8-3C18 core and wind a "primary" of 56 turns and
then continue winding for another 73 turns (autoformer "secondary" of
129 turns), i get about 1800VDC with a doubler (very close to the
peak-to-peak voltage at xfmr output), with a 58Meg load (worst case PMT
divider); voltage at inductor "top" at 30V but can range from about 5V
to 200V (actually more than 200V but my bypass cap is rated at 200V).

** However, nothing you have mentioned addresses any of the major
discrepancies seen.

Tue May 31, 2005 2:47 pm   

Robert,


But that doesn't remove the capacitance that's already
swamping the circuit. The problem is the circuit design,
not the models.


That one works. Notice that that SMPS topology is
a boost. To get higher output voltage, you might try
a tapped-inductor boost. That will reduce the voltage
rating required of the MOSFET and make the circuit
less sensitive to its capacitance. If you're not really
after a SMPS, but some high impedance high voltage,
you can probably get a chopped square wave working
into a diode voltage multiplier to work. That gets rid
of the problem of getting high impedance energy
storage inductors with little stray capacitance.

-Mike

Tue May 31, 2005 6:15 pm   

Mike Engelhardt wrote:

Both theory and practice show that when a voltage is presented across
an inductor, that the current starts at zero and increases in the
standard L/R exponential "decay" to maximum, the assumption is a linear
inductor. Classical definition of an inductor!
The problem, is that the model does *not* show that.
And a pF or two cannot "swamp" anything here.


Ferroxcube 14/8-3C81 core with 56 turns pri and 129 total (secondary),
and get about 1800V DC with about 58Meg load.
Inductor supply can run from about 5V to 200V (bypass cap rating);
looks like i could get up to a 400V input.

I tried the square wave idea (variable amplitude, variable frequency)
idea with a CFL transformer.
Worked fine, efficency improved as i drove it from 1/7, to 1/5, to
1/3 and at "resonance".
Those transformers are very lossy at "high" frequencies; resonance
near 300KHz for the Cooper CTX210407 and two other randomly chosen CFL
xfmrs.
Input square wave, output slightly clipped sinewave; re-winding the
primary drive made no major difference, except with fine wire and many
turns, i saw I*I*R losses (efficency went from 30 percent area to 16
percent).

BUT. Again, there was *no* instant current spike in the amps; there
is clearly an error in the modeling, and i do not see it.

Tue May 31, 2005 8:00 pm   

Robert,


The current does ramp in the inductor when there's voltage
across it in the simulation. But the capacitance(and other
problems) prevents your circuit "design" from working.

Anyway, the "design" you have will not work. The simulation
is correct. If you build it, you will see the same waveforms
as in the simulation until the MOSFET dies due to being
over-voltaged. MOSFET catastrophic failure is not modeled
in LTspice in hope that this allows you to separately debug
the design and then find parts that don't die in the
circuit's operation.


Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

Regards,

--Mike

Tue May 31, 2005 8:14 pm   

On Tue, 31 May 2005 21:00:23 GMT, "Mike Engelhardt" <nospam_at_spam.org>
wrote:


"Designers" are what keep me in the "chips" ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Tue May 31, 2005 8:31 pm   

Robert,


Not a pF or two. A 1.5nF for the MOSFET and 126pF
for the diode. It's hard to run a power SMPS down to
the tiny currents you're trying to do.

It might be illustrative to see your circuit operate
without the capacitance so severely swamping the
circuit. Below is your circuit except ideal switches
are used and the SMPS topology is corrected to a
true boost. This is not a practical circuit design,
because you can't buy the parts to make it go, but
a tapped boost topology would remove the problem
of the MOSFET capacitance.

Regards,

--Mike

Version 4
SHEET 1 1132 680
WIRE -432 -48 -432 -96
WIRE -432 96 -432 32
WIRE -352 96 -352 32
WIRE -352 224 -352 176
WIRE -352 256 -352 224
WIRE -352 368 -352 336
WIRE -240 368 -240 304
WIRE -240 528 -240 432
WIRE -160 -96 -432 -96
WIRE -160 -80 -160 -96
WIRE -160 144 -160 0
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WIRE -144 432 -144 416
WIRE -144 528 -240 528
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TEXT 112 504 Left 0 !.tran 5m startup
TEXT 112 536 Left 0 !.model X D(Ron=1 Roff=1T)
TEXT 112 568 Left 0 !.model SW SW(Ron=1 Roff=1G Vt=5 Vh=-4)

Tue May 31, 2005 8:39 pm   

Mike Engelhardt wrote:


Neither my model nor the "1619" model show a current ramp, period.
I took a simple test fixture that uses a FET with the drain to a fat
wire just long enough for a Tek current probe, then to the test
inductor, then to bypassing, where the inductor supply voltage is applied.
The gate is driven by an HP3312A waveform generator; adjustable rep
rate and pulse width.
Using a 10uH inductor (closest i had to the 12uH in the "1619"
model), and a 3.30V supply, i saw the following:
1) IRFBG20, 1000V rating, "miller" 22nCoul: linear current *ramp* to
600nSec, 60ma at 300nSec. Gate off at 500nSec was "slow" with a sloppy
flyback 20V rounded pulse.
2) IRLZ24N, 55V rating, "miller" 8.5nCoul: linear current *ramp* to
600nSec, 70ma at 300nSec. Gate off at 500nSec was fairly snappy with a
classic flyback 34V flattish pulse.
Case #2 works closer to theory for two reasons: a) the FET is turned
on harder with a 10V gate drive because it is a logic FET, and b) lower
miller capacitance makes for faster turnoff.

The models show *square waves* !!
The models show *AMPS* of current !!
The model does not show anything near reality!
The classic definition of an inductor is a (linear) component that
opposes a change of current.

Tue May 31, 2005 8:42 pm   

Jim Thompson wrote:


If you can tell me what i did wrong in the model, please let me know.
Once the model shows real current ramping in an inductor, then i
think that the rest will be OK.

Tue May 31, 2005 8:46 pm   

On Tue, 31 May 2005 21:42:58 GMT, Robert Baer
<robertbaer_at_earthlink.net> wrote:


Have you checked your _simulated_ schematic against the hardware?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

Tue May 31, 2005 8:55 pm   

"Robert Baer" <robertbaer_at_earthlink.net> schrieb im Newsbeitrag
news:76Xme.29$W77.9_at_newsread3.news.pas.earthlink.net...

Hello Robert,
I did some more simulations with some components changed to get
more reliable results.
Maybe I see now what you mean with wrong pulses.
My simulation has shown double pulses at the gate output of
the LT1619 where I hadn't expected it.

I have sent my results to Mike.
Let's see what he will tell me.

Best regards,
Helmut

Tue May 31, 2005 9:09 pm   

"Helmut Sennewald" <helmutsennewald_at_t-online.de> schrieb im Newsbeitrag
news:d7imh7$vhi$04$1_at_news.t-online.com...

Hello Robert,

I already have got an answer from Mike. He told me
that these complex output pulses may be caused by different
reasons.

Best regards,
Helmut

------- Begin answer from Mike --------

That happens in really bad SMPS designs.
There's lots of ways you can get double/triple
pulses that are due to design flaw(s).
You have to deal with minimum on time,
maximum off time, slope compensation,
capacitive current spikes, blanking times,
and loop instabilities. SMPS have all sorts
of non-linear oscillation modes.

-------- End answer from mike -------------