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analog
Guest
Wed Jun 01, 2005 1:08 pm
Robert Baer wrote:
Quote:
My simplified model uses no LT controllers, so that start-up
business is not present. Just a simple pulse generator driving
a simple FEt to switch an inductor. Modified the generic FET,
as i found that it does not work.
.model IRFBG20 VDMOS(Rg=3 Vto=3.8 Rd=3.6m Rs=2.7m Rb=5m Kp=120
Cgdmax=700p Cgdmin=30p Cgs=900p Cjo=200p Is=68p
mfg=International_Rectifier Vds=1000 Ron=6 Qg=25n)
Robert, I tried your model in your pulse circuit (posted previously
to JT higher in the thread) and it works exactly as expected. The
current ramps up to about 190ma at turn off after which the voltage
rings up to about 900 volts and back down to zero again. Perfect.
By the way (not that it makes any difference to your test case),
your model has unrealistically small resistances throughout (you
have milliohms where you probably meant to have ohms).
Here is your test schematic (slightly redrawn - mind the word
wrap in the model statement at the end):
~~~~~~~~~~~~~~~~~~~~~~~~ Bad_Baer.asc ~~~~~~~~~~~~~~~~~~~~~~~~~~~
Version 4
SHEET 1 1184 680
WIRE 0 128 0 112
WIRE 0 224 0 208
WIRE 0 320 0 304
WIRE 0 416 0 400
WIRE 64 112 0 112
WIRE 64 304 0 304
WIRE 80 304 64 304
WIRE 128 112 64 112
WIRE 128 128 128 112
WIRE 128 224 128 208
WIRE 128 240 128 224
WIRE 144 224 128 224
FLAG 0 224 0
FLAG 128 320 0
FLAG 0 416 0
FLAG 64 112 in
FLAG 144 224 D
FLAG 64 304 G
SYMBOL voltage 0 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 33 32 Left 0
WINDOW 3 33 80 Left 0
SYMATTR InstName V1
SYMATTR Value 10V
SYMBOL ind 112 112 R0
SYMATTR InstName L1
SYMATTR Value 1000µH
SYMBOL nmos 80 224 R0
SYMATTR InstName M1
SYMATTR Value IRFBG20
SYMBOL voltage 0 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 34 32 Left 0
WINDOW 3 31 82 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 10n 10n 19u98 100u)
TEXT 262 154 Left 0 !.tran 0 25u 0 .1u uic
TEXT 264 208 Left 0 ;IRFBG20: Vds=1000 Ron=6 Qg=25n
TEXT 264 256 Left 0 !.model IRFBG20 vdmos(Rg=3 Vto=3.8 Rd=3.6 Rs=2.7 Kp=120 \n+ Cgdmax=0n7 Cgdmin=30p Cgs=0n9 Cjo=0n2 Is=68p Rb=5)
Mike Engelhardt
Guest
Wed Jun 01, 2005 1:26 pm
Robert,
Quote:
I can only tell what the problem is, you have
to do a bit of effort, say, running the
corrected circuit as I posted.
I have run every circuit you gave.
And still don't see it working and still have trouble
with LTspice's solution.
Look, you've not been posting your schematic "work"
lately, so I can't fix any new problems you're introducing,
but going back to your original circuit, the one that
bothers you that there's no ramp in the inductor, and
assert that LTspice giving the wrong answer, just plot
the voltage across the inductor, I think V(n008,n009)
are the node numbers, but just drag the mouse across
the ends of the inductor to plot the voltage across it.
Then plot the inductor dI/dt with D(I(L1)). The waveforms
overlay, except for some number plotting issues from
LTspice plotting finite differences instead of the
derivative. LTspice is computing the correct solution
there. I can make it look like a ramp, but to do that,
I have to remove the capacitance that you've shorted
the thing out with. I have you two examples showing
ramps in the inductor.
Here's the deal: LTspice has corrected computed
the solution of every circuit posted in this thread.
You might need to get the guy who designed the circuit
you've got working on the bench to explain it to you.
I'm not getting through.
--Mike
Mike Engelhardt
Guest
Wed Jun 01, 2005 1:34 pm
Robert,
Quote:
I'm busy, so it may take a few days, but I'll give it a
try in PSpice.
I found the problem in the LTspice circuit...the
"generic" FET isn't complete enough to work.
I added the IRFBG20 as best as i could to the FET library,
using: .model IRFBG20 VDMOS(Rg=3 Vto=3.8 Rd=3.6m Rs=2.7m
Rb=5m Kp=120 Cgdmax=700p Cgdmin=30p Cgs=900p Cjo=200p
Is=68p mfg=International_Rectifier Vds=1000 Ron=6 Qg=25n)
Now that a *specific* FET is there the simple model works!
Oh, that's a mistake I've seen before. It's not a "generic"
FET but the default FET. LTspice uses the same default FET
as other SPICE's. They're conventions to follow or you'll
mess up the people that know what they're doing. The default
SPICE FET is what you might have for one of those monolithic
FET's lithographed on an IC, not a power MOSFET.
But you never posted this error so we couldn't help you with
that. The circuit you posted has shorted out the circuit
with capacitance. The design simply did not work and LTspice
faithfully let you know it in no uncertain terms.
Regards,
--Mike
Genome
Guest
Wed Jun 01, 2005 1:58 pm
"Robert Baer" <robertbaer_at_earthlink.net> wrote in message
news:d8Lme.3891$MI4.26_at_newsread2.news.pas.earthlink.net...
Quote:
The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:
You are an idiot, that's what is wrong.
What does C3 and D2 do in your circuit......?
You think it's some clever sort of voltage doubler type thing, don't you?
Ask yourself what happens when C3 has charged up to some voltage and you
switch the mosfet on.... That's right, D2 becomes forward biased and C3 gets
shorted out through D2 and the mosfet. You get a BIG spike on your current
sense resistor.
Fortunately the LT1619 ignores this because it has leading edge blanking.
So..... that pisses that one off.
You get the drain waveform you get because at start up you are charging the
output capacitors. Do you need a slap around the head to understand that
one.
Another one pissed off.
If you run your circuit for a while so things come into regulation you get
double pulses because you haven't bothered to compensate things properly,
you just pulled values off the data sheet. I'm sure you don't know how.
Probably won't work without a reasonable load anyway.
It's unstable.....
Your last one pissed off.
Let's face it, you design shit because you don't know shit. You also draw
shit circuits. I don't care if you've got something on the bench that works,
it might do but....... it's shit.
I'm the sort of poor sod who gets the job after you've been fucked off and
then I have to fix your shit which is in production and top bosswank, your
bum chum, cannot believe that there is more to it than changing the value of
RZZZ111A.
Tell me where you work so I don't have to go through it again.
And stop blaming your inadequacies on other people. That's my tactic.
Mike and Helmut have missed the bit about your concept of a voltage doubler
but the rest of the advice they are giving you is good. These are two
exceptionally tolerant (and clever) people.
I am not so...... Fuck You.
Here's my contribution...... I will warn you that I have waved my wet finger
in the air to get a result. If I was pushed then I'd do the job right and
provide supporting information.
Unfortunately you come across as a bleating wanker so I'm not going to waste
my time.
Have a crap day.
DNA
Version 4
SHEET 1 1416 740
WIRE -464 432 -464 -48
WIRE -464 544 -464 512
WIRE -464 576 -464 544
WIRE -272 0 -320 0
WIRE -272 32 -272 0
WIRE -272 192 -320 192
WIRE -272 192 -272 112
WIRE -272 224 -272 192
WIRE -272 432 -272 224
WIRE -272 544 -464 544
WIRE -272 544 -272 512
WIRE -160 -48 -464 -48
WIRE -160 32 -160 -48
WIRE -160 144 -160 112
WIRE -144 304 -320 304
WIRE -144 336 -144 304
WIRE -144 432 -144 400
WIRE -144 544 -272 544
WIRE -144 544 -144 512
WIRE -80 144 -160 144
WIRE -80 224 -272 224
WIRE -80 304 -144 304
WIRE 80 -48 -160 -48
WIRE 80 80 80 -48
WIRE 80 544 -144 544
WIRE 80 544 80 368
WIRE 304 -48 80 -48
WIRE 304 144 240 144
WIRE 304 144 304 -48
WIRE 352 432 352 -48
WIRE 352 544 80 544
WIRE 352 544 352 512
WIRE 528 -48 352 -48
WIRE 576 192 512 192
WIRE 576 224 240 224
WIRE 576 224 576 192
WIRE 576 272 512 272
WIRE 576 304 240 304
WIRE 576 304 576 272
WIRE 608 224 576 224
WIRE 720 224 688 224
WIRE 768 -48 608 -48
WIRE 768 96 512 96
WIRE 768 96 768 -48
WIRE 768 144 768 96
WIRE 768 304 576 304
WIRE 768 304 768 240
WIRE 768 432 768 304
WIRE 768 544 352 544
WIRE 768 544 768 512
WIRE 800 -48 768 -48
WIRE 896 -48 864 -48
WIRE 896 432 896 -48
WIRE 896 544 768 544
WIRE 896 544 896 496
WIRE 992 -48 896 -48
WIRE 992 432 992 -48
WIRE 992 544 896 544
WIRE 992 544 992 512
WIRE 1088 -48 992 -48
FLAG -464 576 0
FLAG 512 192 DRV
IOPIN 512 192 In
FLAG 512 96 DRAIN
IOPIN 512 96 Out
FLAG 512 272 ISNS
IOPIN 512 272 Out
FLAG 1088 -48 VOUT
IOPIN 1088 -48 Out
FLAG -320 0 VOUT
IOPIN -320 0 In
FLAG -320 192 VFB
IOPIN -320 192 Out
FLAG -320 304 VERR
IOPIN -320 304 Out
SYMBOL voltage -464 416 R0
WINDOW 0 -120 48 Left 0
WINDOW 3 -120 68 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSUPP
SYMATTR Value 15V
SYMBOL res 752 416 R0
WINDOW 0 -72 45 Left 0
WINDOW 3 -69 70 Left 0
SYMATTR InstName RSNS
SYMATTR Value 0R22
SYMBOL ind 512 -32 R270
WINDOW 3 70 65 VBottom 0
WINDOW 0 65 58 VTop 0
SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 352 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 41 Left 0
WINDOW 3 40 66 Left 0
SYMATTR InstName VBUS
SYMATTR Value 100V
SYMBOL cap 880 432 R0
WINDOW 0 42 24 Left 0
WINDOW 3 41 47 Left 0
SYMATTR InstName C2
SYMATTR Value 4n7
SYMBOL diode 800 -32 R270
WINDOW 0 59 30 VTop 0
WINDOW 3 62 37 VBottom 0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL PowerProducts\\LT1619 80 224 R0
WINDOW 0 -159 -162 Left 0
SYMATTR InstName U1
SYMBOL res -160 416 R0
WINDOW 0 -56 49 Left 0
WINDOW 3 -58 76 Left 0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap -160 336 R0
WINDOW 0 -57 20 Left 0
WINDOW 3 -58 42 Left 0
SYMATTR InstName C1
SYMATTR Value 220p
SYMBOL res -288 416 R0
WINDOW 0 -74 47 Left 0
WINDOW 3 -76 71 Left 0
SYMATTR InstName R2
SYMATTR Value 12.4K
SYMBOL res -288 16 R0
WINDOW 0 -77 45 Left 0
WINDOW 3 -77 71 Left 0
SYMATTR InstName R1
SYMATTR Value 5E6
SYMBOL res -176 16 R0
WINDOW 0 -47 48 Left 0
WINDOW 3 -47 74 Left 0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 976 416 R0
WINDOW 0 39 56 Left 0
SYMATTR InstName RLOAD
SYMATTR Value 100K
SYMBOL nmos 720 144 R0
WINDOW 3 56 61 Left 0
SYMATTR Value Si9420DY
SYMATTR InstName M1
SYMBOL res 704 208 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 10R
TEXT -472 616 Left 0 !.tran 0 250u 10n 10n
Mike Engelhardt
Guest
Wed Jun 01, 2005 3:02 pm
Genome,
Quote:
Mike and Helmut have missed the bit about your concept
of a voltage doubler but the rest of the advice they
are giving you is good. These are two
exceptionally tolerant (and clever) people.
I didn't miss it, I ignored it and changed his
circuit to straight boost in the interest of
simplicity(He had trouble with the relation between
dI/dt and inductance). But yes, you can put a
doubler there on a topology otherwise boost.
Thanks the post!
--Mike
Robert Baer
Guest
Mon Jun 06, 2005 7:31 am
analog wrote:
Quote:
Robert Baer wrote:
My simplified model uses no LT controllers, so that start-up
business is not present. Just a simple pulse generator driving
a simple FEt to switch an inductor. Modified the generic FET,
as i found that it does not work.
.model IRFBG20 VDMOS(Rg=3 Vto=3.8 Rd=3.6m Rs=2.7m Rb=5m Kp=120
Cgdmax=700p Cgdmin=30p Cgs=900p Cjo=200p Is=68p
mfg=International_Rectifier Vds=1000 Ron=6 Qg=25n)
Robert, I tried your model in your pulse circuit (posted previously
to JT higher in the thread) and it works exactly as expected. The
current ramps up to about 190ma at turn off after which the voltage
rings up to about 900 volts and back down to zero again. Perfect.
By the way (not that it makes any difference to your test case),
your model has unrealistically small resistances throughout (you
have milliohms where you probably meant to have ohms).
Here is your test schematic (slightly redrawn - mind the word
wrap in the model statement at the end):
~~~~~~~~~~~~~~~~~~~~~~~~ Bad_Baer.asc ~~~~~~~~~~~~~~~~~~~~~~~~~~~
Version 4
SHEET 1 1184 680
WIRE 0 128 0 112
WIRE 0 224 0 208
WIRE 0 320 0 304
WIRE 0 416 0 400
WIRE 64 112 0 112
WIRE 64 304 0 304
WIRE 80 304 64 304
WIRE 128 112 64 112
WIRE 128 128 128 112
WIRE 128 224 128 208
WIRE 128 240 128 224
WIRE 144 224 128 224
FLAG 0 224 0
FLAG 128 320 0
FLAG 0 416 0
FLAG 64 112 in
FLAG 144 224 D
FLAG 64 304 G
SYMBOL voltage 0 112 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 33 32 Left 0
WINDOW 3 33 80 Left 0
SYMATTR InstName V1
SYMATTR Value 10V
SYMBOL ind 112 112 R0
SYMATTR InstName L1
SYMATTR Value 1000µH
SYMBOL nmos 80 224 R0
SYMATTR InstName M1
SYMATTR Value IRFBG20
SYMBOL voltage 0 304 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 34 32 Left 0
WINDOW 3 31 82 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 10 0 10n 10n 19u98 100u)
TEXT 262 154 Left 0 !.tran 0 25u 0 .1u uic
TEXT 264 208 Left 0 ;IRFBG20: Vds=1000 Ron=6 Qg=25n
TEXT 264 256 Left 0 !.model IRFBG20 vdmos(Rg=3 Vto=3.8 Rd=3.6 Rs=2.7 Kp=120 \n+ Cgdmax=0n7 Cgdmin=30p Cgs=0n9 Cjo=0n2 Is=68p Rb=5)
In "badbaer.asc", i see that the delay in turnoff of the FET (due to
capacitance) is fairly closed to the observed amount.
Robert Baer
Guest
Mon Jun 06, 2005 7:35 am
Genome wrote:
Quote:
"Robert Baer" <robertbaer_at_earthlink.net> wrote in message
news:d8Lme.3891$MI4.26_at_newsread2.news.pas.earthlink.net...
The results are way off.
The sense resistor is for a peak current of 240mA, the time when the
gate is supposed to turn off.
The current in the 1mH inductor is supposed to be a linear ramp from
zero to 240mA, and take about 2.3uSec for an inductor supply of 100V
(8.9uSec for 30V, 5.0uSec for 50V and 1.0uSec for 200V). These values
are from a real circuit, and seem to be reasonably close to calculated
values using E=-L*(dI/dT).
The current never gets into the ampere region(!!).
Furthermore, when the FET turns off, there should be a large, narrow
voltage pulse (not some variable wierd-shaped and slow rise waveform).
What is wrong? Code follows:
You are an idiot, that's what is wrong.
What does C3 and D2 do in your circuit......?
You think it's some clever sort of voltage doubler type thing, don't you?
Ask yourself what happens when C3 has charged up to some voltage and you
switch the mosfet on.... That's right, D2 becomes forward biased and C3 gets
shorted out through D2 and the mosfet. You get a BIG spike on your current
sense resistor.
Fortunately the LT1619 ignores this because it has leading edge blanking.
So..... that pisses that one off.
You get the drain waveform you get because at start up you are charging the
output capacitors. Do you need a slap around the head to understand that
one.
Another one pissed off.
If you run your circuit for a while so things come into regulation you get
double pulses because you haven't bothered to compensate things properly,
you just pulled values off the data sheet. I'm sure you don't know how.
Probably won't work without a reasonable load anyway.
It's unstable.....
Your last one pissed off.
Let's face it, you design shit because you don't know shit. You also draw
shit circuits. I don't care if you've got something on the bench that works,
it might do but....... it's shit.
I'm the sort of poor sod who gets the job after you've been fucked off and
then I have to fix your shit which is in production and top bosswank, your
bum chum, cannot believe that there is more to it than changing the value of
RZZZ111A.
Tell me where you work so I don't have to go through it again.
And stop blaming your inadequacies on other people. That's my tactic.
Mike and Helmut have missed the bit about your concept of a voltage doubler
but the rest of the advice they are giving you is good. These are two
exceptionally tolerant (and clever) people.
I am not so...... Fuck You.
Here's my contribution...... I will warn you that I have waved my wet finger
in the air to get a result. If I was pushed then I'd do the job right and
provide supporting information.
Unfortunately you come across as a bleating wanker so I'm not going to waste
my time.
Have a crap day.
DNA
Version 4
SHEET 1 1416 740
WIRE -464 432 -464 -48
WIRE -464 544 -464 512
WIRE -464 576 -464 544
WIRE -272 0 -320 0
WIRE -272 32 -272 0
WIRE -272 192 -320 192
WIRE -272 192 -272 112
WIRE -272 224 -272 192
WIRE -272 432 -272 224
WIRE -272 544 -464 544
WIRE -272 544 -272 512
WIRE -160 -48 -464 -48
WIRE -160 32 -160 -48
WIRE -160 144 -160 112
WIRE -144 304 -320 304
WIRE -144 336 -144 304
WIRE -144 432 -144 400
WIRE -144 544 -272 544
WIRE -144 544 -144 512
WIRE -80 144 -160 144
WIRE -80 224 -272 224
WIRE -80 304 -144 304
WIRE 80 -48 -160 -48
WIRE 80 80 80 -48
WIRE 80 544 -144 544
WIRE 80 544 80 368
WIRE 304 -48 80 -48
WIRE 304 144 240 144
WIRE 304 144 304 -48
WIRE 352 432 352 -48
WIRE 352 544 80 544
WIRE 352 544 352 512
WIRE 528 -48 352 -48
WIRE 576 192 512 192
WIRE 576 224 240 224
WIRE 576 224 576 192
WIRE 576 272 512 272
WIRE 576 304 240 304
WIRE 576 304 576 272
WIRE 608 224 576 224
WIRE 720 224 688 224
WIRE 768 -48 608 -48
WIRE 768 96 512 96
WIRE 768 96 768 -48
WIRE 768 144 768 96
WIRE 768 304 576 304
WIRE 768 304 768 240
WIRE 768 432 768 304
WIRE 768 544 352 544
WIRE 768 544 768 512
WIRE 800 -48 768 -48
WIRE 896 -48 864 -48
WIRE 896 432 896 -48
WIRE 896 544 768 544
WIRE 896 544 896 496
WIRE 992 -48 896 -48
WIRE 992 432 992 -48
WIRE 992 544 896 544
WIRE 992 544 992 512
WIRE 1088 -48 992 -48
FLAG -464 576 0
FLAG 512 192 DRV
IOPIN 512 192 In
FLAG 512 96 DRAIN
IOPIN 512 96 Out
FLAG 512 272 ISNS
IOPIN 512 272 Out
FLAG 1088 -48 VOUT
IOPIN 1088 -48 Out
FLAG -320 0 VOUT
IOPIN -320 0 In
FLAG -320 192 VFB
IOPIN -320 192 Out
FLAG -320 304 VERR
IOPIN -320 304 Out
SYMBOL voltage -464 416 R0
WINDOW 0 -120 48 Left 0
WINDOW 3 -120 68 Left 0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VSUPP
SYMATTR Value 15V
SYMBOL res 752 416 R0
WINDOW 0 -72 45 Left 0
WINDOW 3 -69 70 Left 0
SYMATTR InstName RSNS
SYMATTR Value 0R22
SYMBOL ind 512 -32 R270
WINDOW 3 70 65 VBottom 0
WINDOW 0 65 58 VTop 0
SYMATTR Value 1mH
SYMATTR InstName L1
SYMBOL voltage 352 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
WINDOW 0 38 41 Left 0
WINDOW 3 40 66 Left 0
SYMATTR InstName VBUS
SYMATTR Value 100V
SYMBOL cap 880 432 R0
WINDOW 0 42 24 Left 0
WINDOW 3 41 47 Left 0
SYMATTR InstName C2
SYMATTR Value 4n7
SYMBOL diode 800 -32 R270
WINDOW 0 59 30 VTop 0
WINDOW 3 62 37 VBottom 0
SYMATTR InstName D1
SYMATTR Value MUR460
SYMBOL PowerProducts\\LT1619 80 224 R0
WINDOW 0 -159 -162 Left 0
SYMATTR InstName U1
SYMBOL res -160 416 R0
WINDOW 0 -56 49 Left 0
WINDOW 3 -58 76 Left 0
SYMATTR InstName R3
SYMATTR Value 100K
SYMBOL cap -160 336 R0
WINDOW 0 -57 20 Left 0
WINDOW 3 -58 42 Left 0
SYMATTR InstName C1
SYMATTR Value 220p
SYMBOL res -288 416 R0
WINDOW 0 -74 47 Left 0
WINDOW 3 -76 71 Left 0
SYMATTR InstName R2
SYMATTR Value 12.4K
SYMBOL res -288 16 R0
WINDOW 0 -77 45 Left 0
WINDOW 3 -77 71 Left 0
SYMATTR InstName R1
SYMATTR Value 5E6
SYMBOL res -176 16 R0
WINDOW 0 -47 48 Left 0
WINDOW 3 -47 74 Left 0
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL res 976 416 R0
WINDOW 0 39 56 Left 0
SYMATTR InstName RLOAD
SYMATTR Value 100K
SYMBOL nmos 720 144 R0
WINDOW 3 56 61 Left 0
SYMATTR Value Si9420DY
SYMATTR InstName M1
SYMBOL res 704 208 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 10R
TEXT -472 616 Left 0 !.tran 0 250u 10n 10n
Look at the 80 to 90 microsecond region; I(l1) and Id(M1) look
reasonable, but V(Isns) looks rather trashy and incorrect.
The drain current in the FET should show up in the source....
legg
Guest
Mon Jun 06, 2005 9:32 am
On Mon, 06 Jun 2005 08:35:52 GMT, Robert Baer
<robertbaer_at_earthlink.net> wrote:
Quote:
Look at the 80 to 90 microsecond region; I(l1) and Id(M1) look
reasonable, but V(Isns) looks rather trashy and incorrect.
The drain current in the FET should show up in the source....
....along with 'some' of the gate current and anything forced in
parallel with DS, when un-enhanced.
It's possible for a model to be more 'accurate' than your observed
scope traces, depending on your selection of model component strays
and the actual physical measurement method used.
RL
xray
Guest
Thu Jun 09, 2005 10:01 am
On Mon, 06 Jun 2005 08:35:52 GMT, Robert Baer <robertbaer_at_earthlink.net>
wrote:
Quote:
Look at the 80 to 90 microsecond region; I(l1) and Id(M1) look
reasonable, but V(Isns) looks rather trashy and incorrect.
The drain current in the FET should show up in the source....
Robert,
Just curious what caused you to stop posting in this thread?
Did Jim T get back to you about PSpice, or did you have a flash of
insight, or did you just get tired?
Curious minds want to know.
Robert Baer
Guest
Sat Jun 11, 2005 7:53 am
xray wrote:
Quote:
On Mon, 06 Jun 2005 08:35:52 GMT, Robert Baer <robertbaer_at_earthlink.net
wrote:
Look at the 80 to 90 microsecond region; I(l1) and Id(M1) look
reasonable, but V(Isns) looks rather trashy and incorrect.
The drain current in the FET should show up in the source....
Robert,
Just curious what caused you to stop posting in this thread?
Did Jim T get back to you about PSpice, or did you have a flash of
insight, or did you just get tired?
Curious minds want to know.
Somewhen i mentioned that after i had a "real" FET model, that Spice
and bench measurements were in reasonable agreement.
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