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Andy
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Sat Jan 23, 2016 12:44 am   



On Monday, January 4, 2016 at 2:01:27 PM UTC-6, rickman wrote:
Rick,

In VHDL, every process is run once at time 0, delta 0, regardless of the sensitivity list.

Thus, even in a clocked process with only the clock in the sensitivity list, it the clock condition does not include the event part, then such a process will run as if clock edge had occurred (if the clock is already '1' at T0,d0).

That may not be how the hardware would behave, and result in simulation mismatches between gate & RTL, or real HW & RTL.

Wait statements are not fooled, nor are if statements if they include the event part.

And if asynchronous reset is used (and reset is in the sensitivity list), then the clock if-statement may evaluate true if there was an event on reset (like a falling edge), while the clock was (already) '1', thus erroneously behaving as if a clock edge was present.

To be safe, and not have different clock-edge-detection conditions for both synchronously and asynchronously reset registers, just include the edge part all the time. And rising_edge()/falling_edge() provide that for you in a much more readable manner.

Andy

Quote:
On 1/4/2016 2:35 PM, Andy wrote:

IEEE STD 1076.6-2004 (IEEE STANDARD FOR VHDL REGISTER TRANSFER LEVEL
SYNTHESIS), Section 6.1.2 Clock Edge Specification, requires both a
level and an event part for the clock specification. Thus either
clock'event or not clock'stable is required.

In a process the clock will be in the sensitivity list. So technically,
doesn't that imply an event any time the process runs?

--

Rick


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