EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

Alliance CAD tool VHDL problem

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - VHDL Language - Alliance CAD tool VHDL problem

yaser fathy
Guest

Fri May 08, 2015 7:46 pm   



Hello,

I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :

the problem is with variable declaration

process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
....

error : ILLEGAL DECLARATION
at the variable declaration line

any help ?

yaser fathy
Guest

Fri May 08, 2015 11:38 pm   



thanks for your reply , but still not working.

GaborSzakacs
Guest

Sat May 09, 2015 12:56 am   



yaser fathy wrote:
Quote:
Hello,

I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :

the problem is with variable declaration

process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
...

error : ILLEGAL DECLARATION
at the variable declaration line

any help ?


Maybe try naming the process, so the variable has an obvious
hierarchical name like:

proc_name: process (CS, wordin, reset)
variable . . .

rickman
Guest

Sat May 09, 2015 4:16 am   



On 5/8/2015 5:38 PM, yaser fathy wrote:
> thanks for your reply , but still not working.

Something else is wrong. It won't be the first time the tool points to
the wrong place to find an error. Check a few lines ahead of the
process declaration. Any mistakes there?

--

Rick

Brian Drummond
Guest

Sat May 09, 2015 12:32 pm   



On Fri, 08 May 2015 10:46:36 -0700, yaser fathy wrote:

Quote:
Hello,

I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here ,


Your code looks OK (from the fragment posted).

How recent is this version of Alliance, how well maintained is it, and
what is its support for newer versions of VHDL?

My understanding is that Alliance is not actively supported, so it may
not understand some perfectly legal constructs used in modern VHDL. (I'd
be delighted f someone told me I'm wrong on this, but I haven't heard of
any recent activity).

-- Brian

yaser fathy
Guest

Sun May 10, 2015 1:11 pm   



the version is 5 copyrighted 2015

if I remove the variable declaration and make a similar signal declaration (before the begin) it compiles and simulates successfully.

yaser fathy
Guest

Sun May 10, 2015 1:13 pm   



the version is 5 copyrighted 2015

if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully.

Gabor
Guest

Mon May 11, 2015 7:30 am   



On 5/10/2015 9:45 PM, Gabor wrote:
Quote:
On 5/10/2015 7:13 AM, yaser fathy wrote:
the version is 5 copyrighted 2015

if I remove the variable declaration and make a similar signal
declaration (before the process) it compiles and simulates successfully.


While that probably is one workaround, you have to be careful
if you start to do this globally on a design. Declaring the
variable outside the process makes it shared, and you want
to be careful not to use it elsewhere. Also you could have
multiple processes with the same name for a local variable,
and you would then have to re-name these when you pull them
out of the process.


OK I see from your new thread that you didn't declare shared variables
but rather signals. You do understand that signals do not take
on their assigned values until the process completes while variables
take on the new value right away? So just moving the declaration
outside the process will change the logic if you make the variable
into a signal.

--
Gabor

Gabor
Guest

Mon May 11, 2015 7:30 am   



On 5/10/2015 7:13 AM, yaser fathy wrote:
Quote:
the version is 5 copyrighted 2015

if I remove the variable declaration and make a similar signal declaration (before the process) it compiles and simulates successfully.


While that probably is one workaround, you have to be careful
if you start to do this globally on a design. Declaring the
variable outside the process makes it shared, and you want
to be careful not to use it elsewhere. Also you could have
multiple processes with the same name for a local variable,
and you would then have to re-name these when you pull them
out of the process.

--
Gabor


Guest

Tue Apr 19, 2016 6:56 pm   



El viernes, 8 de mayo de 2015, 14:46:38 (UTC-3), yaser fathy escribió:
Quote:
Hello,

I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :

the problem is with variable declaration

process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
...

error : ILLEGAL DECLARATION
at the variable declaration line

any help ?


Hi, maybe you code is wrong because you have to declare "variable" like "signal" before the "begin" statement in the architecture declaration and uses in the process, you don't forget that Alliance use VHDL 86 standard. I hope I was usefully. Sorry for my spanglish.
Best Regards
Andrés Rojas


Guest

Fri Apr 22, 2016 2:34 am   



W dniu piątek, 8 maja 2015 19:46:38 UTC+2 użytkownik yaser fathy napisał:
Quote:
Hello,

I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :

the problem is with variable declaration

process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
...

error : ILLEGAL DECLARATION
at the variable declaration line

any help ?


Try:
shared variable addr : std_logic_vector (7 DOWNTO 0);

in architecture declaration.

elektroda.net NewsGroups Forum Index - VHDL Language - Alliance CAD tool VHDL problem

Ask a question - edaboard.com

Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
RTV map EDAboard.com map News map EDAboard.eu map EDAboard.de map EDAboard.co.uk map