Fri Mar 04, 2016 10:26 am
VHDL testbenches very often need better structuring. We should strive for overview, modifiability, extendibility, maintainability and re-use.
We are now posting 3 very easy to understand articles on LinkedIn on how you can achieve this, and of course also increase efficiency and quality significantly. (Using Free, Open source code only)
Please check out: https://www.linkedin.com/pulse/advanced-vhdl-verification-made-simple-anyone-espen-tallaksen?trk=prof-post
Mon Mar 07, 2016 3:40 pm
Am Freitag, 4. März 2016 09:26:39 UTC+1 schrieb espen.t...@bitvis.no:
How about posting here?
Or do you just like to fish for linked-in clicks?
Tue Mar 08, 2016 9:43 am
It was my initial intention to post the whole thing here (in addition to LinkedIn and our own web site). This free and open source VHDL verification framework has received great feedback from VHDL developers, and I assumed it would also be of interest to developers in this forum. I tried to find a way of including figures here - as figures make things very much easier to understand, but it doesn't seem to be possible(?) The alternative was then to post it on bitvis.no. I thought I chose the lesser evil.