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ALuPin
Guest

Tue Jan 06, 2004 8:15 am   



Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????

ALuPin
Guest

Tue Jan 06, 2004 1:29 pm   



Some additional question:
Is the shown macro for functinal or for timing simulation ?
The background of this question: When I run the simulation and
open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
I can find the original names of the primary inputs and outputs
but I can NOT find the original internal names, these seem to be
renamed by the compiler.
If I want to analyse a state machine it is impossible without
the original names.

So my question: How can I simulate (functional) without losing
the original names ?



ALuPin_at_web.de (ALuPin) wrote in message news:<b8a9a7b0.0401052315.f3148fa_at_posting.google.com>...
Quote:
Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????


Mike Treseler
Guest

Tue Jan 06, 2004 7:17 pm   



ALuPin wrote:

Quote:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"

try:

add wave sim:/tb_packetfile_ctrl/u1/*

or from the gui:

view,structure,right-click on u1, add, add to wave

If that doesn't do it, the signal is not there.

Quote:
MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL

Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

-- Mike Treseler

ALuPin
Guest

Wed Jan 07, 2004 8:28 am   



Mike Treseler <mike.treseler_at_flukenetworks.com> wrote in message news:<3FFAFBD0.6050603_at_flukenetworks.com>...
Quote:
ALuPin wrote:

If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"

try:

add wave sim:/tb_packetfile_ctrl/u1/*

or from the gui:

view,structure,right-click on u1, add, add to wave

If that doesn't do it, the signal is not there.

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL

Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

Hi,

what do you mean with "Compile the source files" ?
Compiling the source files in Modelsim or in QuartusII (Processing
->Start Compilation) ?
When I compile the design in QuartusII and use the following (changed)
macro
I cannot find the internal names yet. (like for example last_block).
last_block is visible somehow, but only in combination with different
additional
signals like dataa, datab, datac, datad, aclr, aload, sclr, sload ...

MACRO
cd H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/USB_Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/Data_in
add wave sim:/tb_packetfile_ctrl/u1/Addr_in
add wave sim:/tb_packetfile_ctrl/u1/In_Last_byte
add wave sim:/tb_packetfile_ctrl/u1/Initial_f
add wave sim:/tb_packetfile_ctrl/u1/Data_out
add wave sim:/tb_packetfile_ctrl/u1/Addr_out
run 15000ns

- Andres Vazquez

fe
Guest

Wed Jan 07, 2004 3:42 pm   



Quote:
vcom -93 -reportprogress 300 -work work

{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.

vho}

You must compile in modelsim your rtl file (vhdl source) packetfile_ctrl.vhd
and not the gate file (netlist) packetfile_ctrl.vho produce by quartus after
synthesis.

vcom -93 -reportprogress 300 -work work packetfile_ctrl.vhd

regards
fe

Quote:
vcom -93 -reportprogress 300 -work work

{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CT

RL.vhd}
Quote:
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????


ALuPin
Guest

Thu Jan 08, 2004 8:35 am   



"fe" <notvalid_at_nowhere.com> wrote in message news:<tTUKb.168103$Km5.2182605_at_weber.videotron.net>...
Quote:
vcom -93 -reportprogress 300 -work work

{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.
vho}

You must compile in modelsim your rtl file (vhdl source) packetfile_ctrl.vhd
and not the gate file (netlist) packetfile_ctrl.vho produce by quartus after
synthesis.

vcom -93 -reportprogress 300 -work work packetfile_ctrl.vhd

regards
fe

vcom -93 -reportprogress 300 -work work

{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CT
RL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????


Hi,

thank you for your answer:

The MACRO now looks like that but I still get the following error
message:

"Cannot find QuartusIIVersion3.0(D:/Programme/win32aloem/...altera/Vhdl/src/
altera_mf/altera_mf.vhd)
Source unavailable"

Where could be the problem?
What does "altera_mf.vhd" include?


cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/PACKETFILE_CTRL.vhd}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
run 15000ns


Best regards
Andrés


Guest

Wed Apr 20, 2016 6:17 pm   



On Tuesday, January 6, 2004 at 10:45:12 AM UTC+3:30, ALuPin wrote:
Quote:
Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????


To be able to add internal module signals in ModelSim 10.1c (for example when simulating a test bench module which has not any I/O pins/ports, the internal signals are necessary to be observable) as follows:

1- Start simulation from the Simulate menu by clicking option "Start Simulation..." (not by double clicking on the module).

2- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options..." button. in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)".

GaborSzakacs
Guest

Thu Apr 21, 2016 9:54 pm   



ar.kazemy_at_gmail.com wrote:
Quote:
On Tuesday, January 6, 2004 at 10:45:12 AM UTC+3:30, ALuPin wrote:
Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Thank you for your help.

Best regards
Andrés Vázquez
G&D

MACRO:
cd H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim
vlib modelsim_work
vmap work modelsim_work
vsim -sdftyp /U1=packetfile_ctrl_vhd.sdo work.TB_PACKETFILE_CTRL
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/PACKETFILE_CTRL.vho}
vcom -93 -reportprogress 300 -work work
{H:/EDA/Altera/Extender/Packetfile_Ctrl/simulation/modelsim/TB_PACKETFILE_CTRL.vhd}
view signals
view wave
vsim work.TB_PACKETFILE_CTRL
add wave sim:/tb_packetfile_ctrl/u1/P_clk_in
add wave sim:/tb_packetfile_ctrl/u1/P_clk_out
add wave sim:/tb_packetfile_ctrl/u1/Reset
add wave sim:/tb_packetfile_ctrl/u1/Write
add wave sim:/tb_packetfile_ctrl/u1/Read
add wave sim:/tb_packetfile_ctrl/u1/last_block ?????????????????

To be able to add internal module signals in ModelSim 10.1c (for example when simulating a test bench module which has not any I/O pins/ports, the internal signals are necessary to be observable) as follows:

1- Start simulation from the Simulate menu by clicking option "Start Simulation..." (not by double clicking on the module).

2- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options..." button. in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)".


I don't think Modelsim 10.1 was around in 2004 when that post was written :)

--
Gabor

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