ADC by using counter method on FPGA using VHDL language

Tue Oct 25, 2011 7:58 am   

Hello,i have some idea about vhdl.I want coding of ADC by using
counter method on FPGA by using VHDL.. I know the some idea about this
program the following process.
a) first reset the counter
b)the references and analog voltages are equal then gate can be
closed.then the the value can be stored in the couters i.e., the value
in counter is equavalent to digital value to analog input.
I want coding the above two steps

Tue Oct 25, 2011 3:47 pm   

On Mon, 24 Oct 2011 22:58:59 -0700, VIJAY KUMAR wrote:


A single-slope ADC is probably so easy to code that if you know how to
write the code to use it, the actual ADC logic is trivial.

A dual-slope ADC is nearly so.

So, perhaps you should be inquiring as to how to make a single- or dual-
slope ADC _work_, then just write the code.

--
www.wescottdesign.com

Wed Oct 26, 2011 7:47 am   

On 25 Okt., 07:58, VIJAY KUMAR <jvkphys...@gmail.com> wrote:

Hi Vijay,
please read a little about delta sigma ADCs.
Almost every functional element of these can be done in digital logic
and the theory is well described.
Only a analog comparator and a RC-Lowpass (as DAC for the reference
signal) are needed as external devices.

Have a nice synthesis
Eilert