fofo
Guest
Mon Dec 19, 2011 12:25 pm
Hello,
I'm trying to write a gray counter 4 bits code and what I'm doing is
counting in binary then arranging in gray ^ ^!
This idea, could it be synthesized and how to think physically when
writing HDL codes? then how to check my code for syntax errors???
Thanks a lot
Gabor
Guest
Mon Dec 19, 2011 5:42 pm
fofo wrote:
Quote:
Hello,
I'm trying to write a gray counter 4 bits code and what I'm doing is
counting in binary then arranging in gray ^ ^!
This idea, could it be synthesized and how to think physically when
writing HDL codes? then how to check my code for syntax errors???
Thanks a lot
The main reason to use a Gray code counter is to make sure only one
output changes at a time for ease of crossing clock-domains. If you
have a standard synchronous binary counter and convert its outputs
into Gray code, you don't really have what you want because there
will be decoding glitches on the Gray coded outputs.
So the first thing you need to realize for synthesis is that you
want to preform the binary to Gray conversion on the "next"
binary count state and then register the Gray converted signals
in the same clock domain as the binary count.
This is pretty common technique for building dual-clocked
FIFO's, so you might want to look for FIFO code for
examples.
-- Gabor
